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DDR3 SDRAM模块

于 2023-02-11 发布 文件大小:9.51 kB
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代码说明:

这是DDR3 SDRAM的控制器内核。 默认配置支持一个64位UDIMM或SO-DIMM 支持1GB,2GB,4GB和8GB的DIMM大小 以最低DDR3传输速率600 MT / s工作 针对Xilinx Spartan 6 FPGA系列进行了优化 在不到1300行的Verilog中实现 支持BC4(Burst chop 4)读写命令和刷新命令 XC6SLX25和XC6SLX75 FPGA在-2和-3速度等级下验证了可靠的操作

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