-
Verilog--image-sample
基于Verilog的图像采集、处理和存储程序,初学者参考,高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)
- 2021-04-16 11:48:54下载
- 积分:1
-
zhaozhou_verilog
usb3.0 物理层仿真,verilog编程(Start the physical simulation)
- 2014-04-04 11:49:09下载
- 积分:1
-
MIPSTOP
misp顶层文件,verilog实现misp架构,并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分:1
-
fft_fpga_dit
Decimation-In-Time Fast Fourier Transform
I"ve tried to make the implementation simple and well documented.
I have not tried to make it efficient.
dit.v - Contains main module.
buffer.v - Contains a module for a single butterfly step.
generate_twiddlefactors.py - Contains function to generate a verilog file with twiddlefactors.
twiddlefactors_N.v.t - Template used to generate verilog file.
dut_dit.v - A wrapper around the "dit" module to allow verification with MyHDL.
qa_dit.py - A MyHDL test bench for verification.
Requires MyHDL, iverilog and numpy to be installed.
pyfft.py - Generates output of intermediate FFT stages. Useful for debugging.
- 2022-03-30 05:04:52下载
- 积分:1
-
400rdm
用于FPGA的学习,大家值得借鉴,可以好好学习一下(this is for fpga and you can use this.)
- 2020-06-16 15:20:02下载
- 积分:1
-
firfilter
FIR滤波器:自定滤波器的类型(低通,高通或带通)、设计指标(通带截止频率、通带波纹、阻带截止频率、阻带衰减)
1、根据指标选择合适的窗函数,用窗口设计法设计符合指标的FIR滤波器;并验证其性能是否满足预定指标。
(FIR filters: Custom filter types (low pass, high pass or band-pass), design specifications (passband cutoff frequency, passband ripple, stopband cutoff frequency, stopband attenuation) 1, according to indicators choose the right window function, using the window design method of FIR filter designed to meet the targets and verify that its performance meets the set targets.)
- 2010-01-13 19:14:21下载
- 积分:1
-
BmpDecoder
适用于Altera FPGA Nios II平台uClinux OpenCV之BmpDecoder的源码(Souce code of BmpDecoder for Altera FPGA Nios II uClinux OpenCV)
- 2011-02-11 16:43:45下载
- 积分:1
-
axi_spi_master
arm的axi接口转spi接口master源代码,已经使用过,带注释,
- 2022-03-23 04:14:36下载
- 积分:1
-
exercise3
用verilog实现dsp与Fpga接口的同步设计,其功能包括读写操作及四个功能模块,采用两个fifo实现不同时钟域的地址与数据的转换,在quartus ii11.0环境下运行,运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分:1
-
Verilog 浮点计算
这段代码在 verilog 的用于计算 2 的浮点数,需要计算的保险带的 all32 位,它可以用。
- 2023-05-14 01:20:04下载
- 积分:1