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gcounter1
数字钟vhdl实现，在线测试无误，具有闹钟，对表功能(Digital clock vhdl implementation, online testing is correct, with alarm, the table function)
- 2013-10-19 22:06:16下载
- 积分：1
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StopWatch
This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
- 2013-10-04 00:53:49下载
- 积分：1
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VerilogHdlPracticeAndSystemDesign
本RAR包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。(The RAR includes " Verilog-HDL Practice and Application of system design," a book full of examples, all passed validation. Chapter VII of the future design examples, not only examples of Verilog-HDL, but also attached, including VB, VC++ source code, etc., and even DLL generation methods explained in detail.)
- 2009-11-10 19:40:12下载
- 积分：1
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used in the preparation of Verilog FLEX10K achieve simple CPU
用verilog编写在FLEX10K上实现的简易CPU-used in the preparation of Verilog FLEX10K achieve simple CPU
- 2022-03-25 10:21:37下载
- 积分：1
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h264_intp
图形图像H264插值算法，应用于图像视频处理(H264 graphic image interpolation algorithm is applied to image video processing)
- 2021-05-14 18:30:02下载
- 积分：1
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SineGen
Basic VHDL code to create a sine wave generator for an FPGA board.
- 2014-01-24 01:04:15下载
- 积分：1
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１３键键盘的ＶＨＤＬ顶层文件，我是初学着，希望对初学者有用...
１３键键盘的ＶＨＤＬ顶层文件，我是初学着，希望对初学者有用-13 key keyboard VHDL top-level document, I was a novice with the hope that useful for beginners
- 2022-03-04 05:06:34下载
- 积分：1
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bianyuanjiance
说明： 图像采集 VGA输出 图像的边缘 ov7670(V image acquisition VGA output image edge)
- 2020-06-21 13:20:06下载
- 积分：1
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scan_led
FPGA扫描LED显示灯，动态扫描,进行流水显示(FPGA Scan LED indicator lights, dynamic scanning, make the water show)
- 2015-02-16 18:02:16下载
- 积分：1
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ADC-Parameter
外部ADC采集数据，存为数组文件。通过程序读入，然后即可求出ADC的SNR、SINAD、THD、ENOB等。(External ADC data collection, stored as an array of documents. Read through the program, then the ADC SNR, SINAD, THD, ENOB can be calculated.)
- 2021-03-15 21:39:22下载
- 积分：1
