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CS5532是用来测量ADC芯片的装置，这是中国的声明
Cs5532是一款用于测量仪器的ADC芯片,这是他的中文说明书-Cs5532 is a device used to measure the ADC chip, which is the Chinese statement
- 2022-10-25 01:15:03下载
- 积分：1
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jBpm4.0中文说明文档jBPM4.0GA_zh_CN_by_opug.org.cn_viaREDSAGA.pdf
jBpm4.0中文说明文档jBPM4.0GA_zh_CN_by_opug.org.cn_viaREDSAGA.pdf-jBpm4.0 English documentation jBPM4.0GA_zh_CN_by_opug.org.cn_viaREDSAGA.pdf
- 2023-09-05 03:35:05下载
- 积分：1
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一本好的电子书籍
一本好的电子书籍-a good e-books
- 2022-04-16 13:43:54下载
- 积分：1
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c++ program design(third edition) c++ 程序设计(第三版) James P.Cohoon,Jack W.Davidson 著...
c++ program design(third edition) c++ 程序设计(第三版) James P.Cohoon,Jack W.Davidson 著 刘瑞挺 韩毅刚 盛素英 刘海嘉 译 电子工业出版社, 麦格劳-希尔教育出版集团 2002年1月-(third edition) c Program Design (third edition) James P. Cohoon, Jack W. Davidson with LIU Hanyigang Sheng-Ting Ying Liuhaijia Translation Publishing House of Electronics Industry, McGraw-Hill Education Publishing Group in January 2002
- 2022-11-17 16:20:03下载
- 积分：1
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数字水印技术综述
Digital Watermarking Survey
- 2023-02-11 11:55:04下载
- 积分：1
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用简单的方法分类高速公路上下行数据集
使用简单的方法，分类了G4高速公路湖南段的数据，并利用pyecharts进行了可视化
- 2022-05-29 07:31:49下载
- 积分：1
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该教程浅显易懂,讲解透彻,是一本不错的教程
该教程浅显易懂,讲解透彻,是一本不错的教程- This course simple easy to understand, the explanation is
thorough, is a good course
- 2023-01-28 01:10:03下载
- 积分：1
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看一下吧。
不过说实话，我是为了满足个源码才传的这个。
由于很多源码没有整理，所以不敢乱传。
以后我会多多的上传的。（不过站长可得让我也下载哟^_^...
看一下吧。
不过说实话，我是为了满足个源码才传的这个。
由于很多源码没有整理，所以不敢乱传。
以后我会多多的上传的。（不过站长可得让我也下载哟^_^）-Look at it. But I can honestly say that I was only in order to meet a source of this mass. As a result of not finishing a lot of source code, I do not mass chaos. Later I will upload all sorts. (Although regulators may have to let me download yo ^ _ ^)
- 2022-02-10 09:20:08下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
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C_C++常见bug的书
C_C++常见bug的书-1，对于调试中碰到的问题很有帮助-C_C common bug book-1 for debugging problems they encountered in helpful
- 2023-02-27 17:55:03下载
- 积分：1
