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AD_sample
AD采集模块,设计模块采集AD5270的输出数据(AD Collection module
Design module to collect the output data of AD5270
)
- 2020-11-18 16:19:39下载
- 积分:1
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RS232 communication protocol with the VHDL language, based on the Altium Designe...
此RS232通信协议用VHDL语言实现,基于Altium Designer公司的Protel DXP开发平台。本人是基于Nanaboard开发板编写的程序,其他用户只需要对配置文件进行修改即可用于其他电路板。-RS232 communication protocol with the VHDL language, based on the Altium Designer
- 2023-01-28 04:55:04下载
- 积分:1
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数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;...
数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;
- 2023-07-21 04:20:04下载
- 积分:1
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Риторика_Зачетная работа
access must be conf urr arr
- 2019-05-29 20:23:53下载
- 积分:1
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16位元浮点数CPU,可作运算,以VHDL编写
16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL
- 2022-05-17 06:20:07下载
- 积分:1
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曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0,低→ 高的跳变表示为1。每个码元中间都要发生跳变,接收端可将此变化提取...
曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0,低→ 高的跳变表示为1。每个码元中间都要发生跳变,接收端可将此变化提取出来作为同步信号,使接收端的时钟与发送设备的时钟保持一致-Manchester coding techniques that use voltage changes in 0 and 1. Provisions in the middle of each symbol hopping happen. High → low hopping express 0, low → high jump for the express one. Symbol between each transition must happen, this change in the receiver can be extracted as a synchronization signal to the receiving end of the clock and send the equipment to maintain the same clock
- 2023-06-17 15:30:03下载
- 积分:1
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Altera Corporation for DE2 development board of the TV demonstration
用于Altera公司DE2开发板的TV demonstration-Altera Corporation for DE2 development board of the TV demonstration
- 2022-03-26 12:20:58下载
- 积分:1
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浮点数运算的FPGA实现,包括仿真文件。
浮点数运算的FPGA实现,包括仿真文件。-FPGA realization of floating-point operations, including the simulation file
- 2022-07-18 19:56:21下载
- 积分:1
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vote7
说明: 自己设计的一个其人投票系统,对于VHDL初学者可以参考下(One of their own design their human voting system, for VHDL beginners can refer to the following)
- 2009-08-30 09:25:04下载
- 积分:1
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VGA采用Spartan 3E板系统的VHDL
Vga in vhdl using spartan 3e board basys
- 2023-04-03 19:05:04下载
- 积分:1