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uart_byte_rx
说明: libero soc工程,实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)
- 2020-06-21 09:20:01下载
- 积分:1
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8253
8253可编程定时器/计数器芯片 VeriLog实现(8253 programmable timer/counter chip VeriLog achieve)
- 2013-05-31 20:40:23下载
- 积分:1
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AD7980
AD9850 VERILOG代码 硬件验证过,可以使用。
- 2021-05-07 15:37:36下载
- 积分:1
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ds312_Spartan-3E-FPGA
FPGA资料与所用元器件的数据参考手册与应用指南(ds312_Spartan-3E FPGA Family )
- 2012-09-18 21:43:54下载
- 积分:1
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fft
说明: 用FPGA实现8点fft,整个代码使用verilog编写,主要运用了加法器和乘法器,简单易懂(8-point FFT with FPGA, The whole code is written by Verilog, mainly using adder and multiplier, which is easy to understand)
- 2021-03-29 20:59:10下载
- 积分:1
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rs_204_188----v1.0
RS 编码和解码Verilog Code, 实现了RS(204,188)的编码和译码;(RS Coding and Decoding Verilog code, implement RS(204,188) )
- 2021-03-25 20:29:14下载
- 积分:1
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biaojue4
此代码实现4人表决功能,4人中有三人同意即为通过。(Four voting)
- 2013-10-29 21:46:07下载
- 积分:1
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RANGEN
2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码,verilog编写;包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)
- 2020-10-27 17:09:59下载
- 积分:1
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clock
EDA用maxplus2开发设计的简易数字钟,适合初学者,vhdL语言(EDA maxplus2 in development and design of simple digital clock, is suitable for beginners, vhdL language
)
- 2011-10-03 20:50:23下载
- 积分:1
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Single-CPU
说明: 简单的单周期CPU设计,实现的指令有:算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)
- 2020-06-16 12:28:32下载
- 积分:1