网站首页

Commonly used phase

于 2022-10-15 发布文件大小:2.56 kB

 0  53

下载积分: 2 下载次数: 1

我要下载

代码说明：

常用的锁相环技术，此程序是我在设计高频电路中运用的，具体见程序，经调试无问题-Commonly used phase-locked loop technology, this program is in the design I used in high-frequency circuits, see the specific procedures, no problem by debugging

下载说明：请别用迅雷下载，失败请重下，重下不扣分！

发表评论

0 个回复

CalcJavaCRC
This programa execute calc of CRC by use a table.

2014-08-21 23:04:30下载

积分：1
UART
说明：使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。(The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.)

2008-10-09 15:59:20下载

积分：1
Timing_Closure
详细讲解时序约束培训教材，有利于更好对时序约束的理解(Timing constraints elaborate training materials, facilitate better understanding of the timing constraints)

2010-08-12 20:02:33下载

积分：1
uart
用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。(a veriog program completed on FPGA to contrlo a uart to communicaton with a computer )

2010-08-16 10:41:03下载

积分：1
canny
说明： canny 边缘检测基于梯度直方图的自适应阈值verilog实现(Canny edge detection based on gradient histogram adaptive threshold Verilog implementation)

2021-04-12 14:48:57下载

积分：1
eth_frame_gen
帧激励产生器，用于VMM仿真中生成所需要帧以供测试所用(the use for test)

2012-02-02 22:19:25下载

积分：1
DATA_scramble
扰码器的verilog实现,参考802.11a相关标准(Scrambler in verilog implementation)

2009-12-20 16:44:15下载

积分：1
一个可用的很不错的DDS 频率合成程序，用VHDL语言编写
一个可用的很不错的DDS 频率合成程序，用VHDL语言编写-Available is a good DDS frequency synthesis procedures, using VHDL language

2022-11-29 23:55:03下载

积分：1
DE2_CCD
说明：此程序用来实现图像的采集和帧数的计算功能。(Image acquisition and calculation of the number of frames.)

2011-04-17 09:43:37下载

积分：1
QAM16_demo
This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery.

2010-11-09 03:00:52下载

积分：1

696518资源总数
104297会员总数
29今日下载

Commonly used phase

0 个回复

热门标签

热门下载