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scia_loopback_interrupts
TI F28027 SCI 源码，中断，FIFO，LoopBack使能(TI F28027 SCI source code, interrupt, FIFO and Loopback enalbe)
- 2020-11-18 15:29:40下载
- 积分：1
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shumagua
通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made into a single-chip digital clock program)
- 2013-10-27 12:30:04下载
- 积分：1
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FIRfilterverilogHDL
FIR滤波器的verilog HDL代码示例，以16阶为例(Verilog HDL code for fir filter)
- 2015-07-08 17:05:38下载
- 积分：1
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FPGA_GFP
基于FPGA的GFP（通用成帧协议）封装数据成帧的实现。(FPGA-based GFP (Generic Framing Protocol) encapsulated data Framing realized.)
- 2007-07-20 15:07:59下载
- 积分：1
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ahb2wishbone_latest.tar
AHB to Wishbone memory interface VHDL source code
- 2013-01-11 11:17:03下载
- 积分：1
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1-Quadrature_decoder
说明： 光栅尺FPGA调试程序，本人亲自调试保证可用(Grating ruler FPGA debugging program)
- 2019-12-31 23:23:11下载
- 积分：1
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multi16
有符号16位乘法器。经典booth编码。拓扑结构为wallance树。加法器类型是进位选择加法器。(Number system: 2 s complement
Multiplicand length: 16
Multiplier length: 16
Partial product generation: PPG with Radix-4 modified Booth recoding
Partial product accumulation: Wallace tree
Final stage addition: Carry select adder
)
- 2013-01-01 14:13:58下载
- 积分：1
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SPI接口代码
对SPI接口的verilog编程，SPI is a simple interface that allows one chip to communicate with one or more other chips.
- 2022-04-16 11:02:29下载
- 积分：1
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new
说明： vivado2017.4下的串口通信的Verilog源码，一次传输8位，包括发送模块，接受模块，顶层模块(Verilog source code for serial communication under vivado 2017.4, which transmits 8 bits at a time, including sending module, receiving module and top module)
- 2020-06-22 20:20:01下载
- 积分：1
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jiaotongdeng
Quartus2环境下基于VHDL状态机的交通灯程序(VHDL state machine traffic lights based on Quartus2 environment)
- 2014-01-13 21:57:00下载
- 积分：1
