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UART_Test
OMAP5912 UART的测试程序 包括头文件 源文件等。(OMAP5912 UART program test)
- 2011-08-14 16:04:03下载
- 积分:1
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一种接口控制板的逻辑电路设计CPLD程序。
一种接口控制板的逻辑电路设计CPLD程序。-an interface to the control board CPLD logic circuit design process.
- 2022-06-19 00:18:27下载
- 积分:1
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嵌入式应用开发技术白金手册源代码
嵌入式应用开发技术白金手源代码...
嵌入式应用开发技术白金手册源代码
嵌入式应用开发技术白金手源代码-this is a vhdf code
- 2022-04-28 14:40:01下载
- 积分:1
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8 位 CPU vhdl实现(含全部源代码)
说明: 这是8位CPU的CVDL代码。CPU 的主要功能是执行指令,控制完成计算机的各项操作,包括运算操作、传送操作、输入/输出操作等。作为模型计算机设计,将重点放在寄存器级,采取较简单的组成模式,以尽量简洁的设计帮助学生掌握CPU 的基本原理。 此次设计CPU就是为了了解CPU运行的原理,从而完成从指令系统到CPU的设计,并且通过仿真对CPU设计进行正确性评定。(The main function of CPU is to execute instructions, control and complete various operations of computer, including operation, transfer operation, input / output operation, etc. As a model computer design, it focuses on register level and adopts a simpler composition mode to help students master the basic principles of CPU with a concise design as far as possible. This design of CPU is to understand the principle of CPU operation, so as to complete the design from instruction system to CPU, and evaluate the correctness of CPU design through simulation.)
- 2020-12-09 15:49:20下载
- 积分:1
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verilog写的数字频率计的显示模块,可以
verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be
- 2022-03-23 18:10:33下载
- 积分:1
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taxi
利用Verilog HDL语言设计了出租车计费器,使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能,并设置了动态扫描电路显示车费和对应时间,显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。(Design using Verilog HDL language a taxi meter, it has time display, billing and simulation taxi start, stop, reset and other functions, and set dynamically display scanning circuit and the corresponding time fare, shows the hardware description language Verilog-HDL design advantages of digital logic circuits.)
- 2011-08-30 08:18:51下载
- 积分:1
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alu
the 8 bit alu by verilog
- 2011-05-26 11:25:43下载
- 积分:1
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n_bit_paralleLoadShiftRegJK
n_bit_paralleLoadShiftRegJK
- 2017-11-17 17:27:49下载
- 积分:1
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关于寄存器重命名register reallocation,VHDL
关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL
- 2022-02-09 20:31:31下载
- 积分:1
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用于FPGA的huffman算法的HDL编码
用于FPGA的huffman算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。(The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.)
- 2008-08-01 17:25:44下载
- 积分:1