-
UART_FPGA
此vhdl程序实现了在FPGA上构建UART通信串口。分为两部分，UART的发送端transfer和接收端receiver。需要外部根据需求提供波特率时钟。(This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the baud clock external demand.)
- 2015-03-04 11:02:17下载
- 积分：1
-
simpleCpu
relative cpu design implementation
- 2013-08-14 21:22:39下载
- 积分：1
-
video_avg33_filter
图片采用3x3均值滤波，用Verilog语言描述，输入输出分别使用外同步(Pictures are filtered with 3x3 mean and described in Verilog language. Input and output are synchronized with each other.)
- 2019-06-03 13:54:54下载
- 积分：1
-
H.265视频压缩的FPGA实现
说明： 使用verilog语言实现H.265压缩算法，能够实现实时视频数据的压缩传输(Using Verilog language to realize h.265 compression algorithm can realize the compression and transmission of real-time video data)
- 2020-06-29 02:40:01下载
- 积分：1
-
MAX262
MAX262是一款可程控滤波芯片,该是它的英文数据手册.(MAX262 is a programmable filter chip, which is its data sheet in English.)
- 2007-08-14 16:32:01下载
- 积分：1
-
LCD12864
verilog lcd2864 适合初学者(verilog lcd2864 )
- 2013-10-15 18:57:45下载
- 积分：1
-
中值滤波算法
中值滤波实现。选择在Vivado软件上采用Verilog语言来编写中值滤波算法，搭建出完整的数据处理系统架构，通过仿真和验证来判断数据的处理效果，并在实际的设计过程中根据出现的问题提出解决方案。(Median filter implementation. The author chose Verilog language to write the median filter algorithm in Vivado software, built a complete data processing system architecture, judged the data processing effect through simulation and verification, and proposed a solution according to the problems in the actual design process.)
- 2018-05-30 13:44:03下载
- 积分：1
-
I121-v1.10
Implementation of Serial Infrared decoder for low-speed IrDA communications.
- 2013-06-14 05:38:14下载
- 积分：1
-
xilinx_edk_9.2_crack
xilinx edk 9.2 破解器/注册机(xilinx edk 9.2 crack)
- 2021-03-29 15:09:10下载
- 积分：1
-
TLC5510
TLC5510的驱动程序，采用Verilog语言编写(TLC5510 driver, the use of Verilog language)
- 2020-08-13 21:38:29下载
- 积分：1
