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EDA VHDL modules commonly used procedure, the time
EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)
- 2022-07-02 21:52:46下载
- 积分：1
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gtx_aurora_zc706_clock_module
对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)
- 2018-01-23 09:03:31下载
- 积分：1
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DDS
Verilog实现DDS线性调频，Verilog实现DDS线性调频(Verilog implementation of DDS linear FM，Verilog implementation of DDS linear FM)
- 2015-07-29 19:59:36下载
- 积分：1
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AD7991_7995_7999
AD7991_7995_7999转换器说明(4-Channel, 12-/10-/8-Bit ADC with
I2C-Compatible Interface in 8-Lead SOT-23)
- 2013-05-15 20:14:11下载
- 积分：1
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FPGA design of a full set of frequency data, I hope all of you ah like useful
FPGA设计频率计全套资料，我希望对大家啊好似有用的-FPGA design of a full set of frequency data, I hope all of you ah like useful
- 2023-01-04 19:10:03下载
- 积分：1
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sqr
VHDL CODE FOR SQUARE WAVE GENERATOR
- 2014-01-22 17:14:20下载
- 积分：1
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proj-ASC
simple microprocessor that gives the greatest common divisor of 2 (4bit) numbers
- 2014-11-05 06:32:53下载
- 积分：1
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wireless_communication
无线通信调制解调用的verlog和matlab程序，很大很实用。(Wireless modem calls verlog and matlab program, very very practical.)
- 2010-05-31 10:01:18下载
- 积分：1
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vibration-test-for-shafting-system
轴系测试程序，多通道输入输出，实现时域、频域、轴心轨迹、瀑布图等功能。(Shafting test program, multi-channel input and output, to achieve time domain, frequency domain, orbit, waterfall and other functions.)
- 2013-06-28 16:20:50下载
- 积分：1
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Advanced-FPGA-Design
高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)
- 2021-04-01 11:09:08下载
- 积分：1
