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DES 硬件实现
AES的Verilog实现源码,速度还可以,s盒使用case实现的,testbench的测试数据有2百多,已经过验证。在DC 下跑到800mHZ.
- 2022-05-13 06:06:08下载
- 积分:1
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SMBus
SMBus控制器的VHDL源码程序,适用于Quartus2,ISE等开发环境。(The SMBus controller VHDL source code procedures applicable to Quartus2 ISE development environment.)
- 2021-03-24 18:39:14下载
- 积分:1
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ppm解码器
说明: 使用verilog实现ppm解码器,功能仿真通过,附设计说明,THU微纳电子系ic设计课大作业。(a ppm decoder written in VerilogHDL, a design document is available)
- 2020-11-26 20:09:31下载
- 积分:1
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chengxu
数字时钟,可以实现(1) 显示日期功能(年、月、日、时、分、秒以及)
(2) 可通过按键切换年、月、日及时、分、秒的显示状态
(3) 可随时调校年、月、日或时、分、秒
(4) 可每次增减一进行时间调节
(5) 可动态完整显示年份,实现真正的万年历显示
(6) 可显示温度
(Digital clock, can be achieved (1) the date function (year, month, day, hour, minute, seconds as well) (2) through the key switch the year, month, day in a timely manner, minute, second display state (3) at any time adjust the year, month, day or time, minutes, seconds (4) can be added or deleted, a time adjustment (5) can be dynamically complete display Year, the real calendar display (6) to display temperature)
- 2012-10-15 00:25:33下载
- 积分:1
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i2c_master_top
i2c core : i2c master top
- 2012-05-23 01:17:22下载
- 积分:1
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crc8
8位crc的verilog设计 通过仿真综合验证并已应用在工程里面
(verilog of 8bit error checkout )
- 2021-03-01 11:09:34下载
- 积分:1
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uart
说明: uart 发送模块接收模块及tb,其中可以选择不同波特率进行收发,代码带有详细注释。(UART sending module and receiving module)
- 2020-06-20 20:00:02下载
- 积分:1
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clk_div3
在fpga中对于pll无法完成的分频,可采用计数方式,本例用状态机实现对时钟的奇数分频。(Pll in fpga can not be completed in the sub-frequency counting method can be used, in this case with the state machine to achieve an odd number on the clock frequency.)
- 2010-07-28 20:03:41下载
- 积分:1
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Cadence-Allegro-PCB-SI
利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)
- 2013-08-06 22:17:46下载
- 积分:1
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EP3C16_Nios_MMA7455
实现基于NIOS的 EP3C16与加速度传感器NMA7455的IIC基本通信(Realization of based on NIOS EP3C16 and acceleration sensor NMA7455 IIC of basic communication
)
- 2013-01-29 13:22:50下载
- 积分:1