登录
首页 » VHDL » 它执行浮点运算单元

它执行浮点运算单元

于 2022-08-09 发布 文件大小:98.10 kB
0 70
下载积分: 2 下载次数: 1

代码说明:

it performs the floating point arithmetic unit

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论


0 个回复

  • 有业主从PCI PCI、PCI目标是开源的,是项目的发展。
    内有一PCI 主 和PCI从,PCI TARGET 都是公开代码的,是工程文件,有仿真工程,使用说明。觉得好的就推荐一下。 本PCI_HOST目前支持: 1、 对目标PCI_T进行配置; 2、 对目标进行单周期读写; 3、 可以工作在33MHZ和66MHZ 4、 支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的!!!软件里面调试仿真了半天,终于调通了,到了下载就突然弹出窗口说包含了有限制的IP CORE,是限制使用的-There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of
    2022-06-15 03:52:50下载
    积分:1
  • VHDL
    先设计序列发生器产生序列:1011010001101010;再设计序列检测器,检测序列发生器产生序列,若检测到信号与预置待测信号相同,则输出“1”,否则输出“0”,并且将检测到的信号的显示出来。(First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.)
    2015-01-04 12:35:54下载
    积分:1
  • det
    double edfe trigger d latch
    2014-01-07 19:55:29下载
    积分:1
  • sdram_hr_hw_4port
    这个是DE2上的SDRAM 四个端口的驱动代码,相当实用!(This is a four-port SDRAM on a DE2 driver code, very useful!)
    2010-07-14 21:21:05下载
    积分:1
  • 以太网控制器Verilog源码(含有MAC,MII接口)
    以太网控制器Verilog源码(含有MAC,MII接口)(Ethernet controller Verilog source code (including MAC, MII interface))
    2017-08-18 10:32:27下载
    积分:1
  • 《Verilog HDL 程序设计教程》3
    《Verilog HDL 程序设计教程》3-"Verilog HDL Design Guide" 3
    2023-02-08 02:25:03下载
    积分:1
  • 2022-05-01 00:03:25下载
    积分:1
  • 采用Verilog HDL硬件语言设计,实现基本的公用电话计费功能,设计完整....
    采用Verilog HDL硬件语言设计,实现基本的公用电话计费功能,设计完整.-Using Verilog HDL language hardware design, the realization of the basic public telephone billing function, design integrity.
    2022-02-25 23:14:29下载
    积分:1
  • adda
    说明:  基于FPGA 黑金ALINX 515的 ADDA采样模块源码(需调试)(ADDA Sampling Module Source Code Based on FPGA Heijin ALINX 515)
    2020-06-20 13:00:01下载
    积分:1
  • Over_Current_Relay_Co_ordination
    try this for pq improvmnett
    2012-11-17 05:40:30下载
    积分:1
  • 696518资源总数
  • 104441会员总数
  • 19今日下载