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Traffic_RYG
说明: 交通灯的控制,分主干道和从路交通灯,主路优先,正常情况下,绿灯60s,红灯30S,黄灯5S(Traffic light control)
- 2020-06-21 06:40:02下载
- 积分:1
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基于FPGA的调制,实现了QPSK调制,所用芯片为Artera的CycloneIIEp2C5T114C8...
基于FPGA的调制,实现了QPSK调制,所用芯片为Artera的CycloneIIEp2C5T114C8-FPGA-based modulation, realize the QPSK modulation, the chip used for Artera
- 2022-06-16 16:50:45下载
- 积分:1
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FDDDDRSDRAMP
一种基于FPGA 实现DDDR SDRAM的控制器
(DDDR SDRAM controller based on FPGA)
- 2012-08-29 23:52:53下载
- 积分:1
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altera公司cpld的原理图库(protel格式)
altera公司cpld的原理图库(protel格式)-sch.lib about altera s cpld.
- 2022-03-18 02:53:20下载
- 积分:1
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BCD_to_7_seg_decoder
BCD to 7 segments display decoder
- 2015-06-15 22:36:01下载
- 积分:1
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程序
说明: 传感器是一种检测装置,能感受到被测量的信息,并能将感受到的信息,按一定规律变换成为电信号或其他所需形式的信息输出,以满足信息的传输、处理、存储、显示、记录和控制等要求(Sensor is a kind of detection device, which can sense the measured information and transform it into electrical signal or other required information output according to certain rules to meet the requirements of information transmission, processing, storage, display, recording and control.)
- 2020-06-18 22:00:01下载
- 积分:1
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tdc
time to digital convertor
- 2011-09-22 16:25:50下载
- 积分:1
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用VHDL语言设计分频器,主要是因为一些子
使用VHDL进行分频器设计,主要是一些分频的东西,整数分频,小数分频,奇次分频和偶次分频-Divider using VHDL to design, mainly because some sub-band stuff, integer divider, fractional-N, odd and even sub-sub-sub-sub-band frequency
- 2022-04-24 21:36:07下载
- 积分:1
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full adder设计代码,verilog 语言描述,通过modelsim 仿真,quartus综合...
full adder设计代码,verilog 语言描述,通过modelsim 仿真,quartus综合-full adder design code, verilog language to describe, through the ModelSim simulation, quartus integrated
- 2022-06-30 03:26:15下载
- 积分:1
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CAM
Content-addressable memory (CAM) is a special type of computer memory used in certain very-high-speed searching applications. It is also known as associative memory, associative storage, or associative array, although the last term is more often used for a programming data structure.
- 2014-12-06 00:33:45下载
- 积分:1