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用VERILOG语言编写的电子琴程序.用GW48教学实验箱仿真的
用VERILOG语言编写的电子琴程序.用GW48教学实验箱仿真的-Using Verilog language organ procedures. GW48 teaching experiment with simulation boxes
- 2022-03-01 23:12:48下载
- 积分：1
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波形发生器，带TESTBENCH，
多平台
波形发生器，带TESTBENCH，
多平台
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
-waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn
- 2023-05-18 16:15:03下载
- 积分：1
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I2C_CSDN
说明： verilog 编写的I2C程序，控制D/A的(I2C program written by Verilog to control D/A)
- 2020-06-18 21:20:02下载
- 积分：1
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pl_read_write_ps_ddr
说明： PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重，常常需要将 PL 端的大量数据实时送到 PS 端处理，或者将 PS 端处理结果实时送到 PL 端处理，但是各种协议非常麻烦，灵活性也比较差，直接通过 AXI 总线来读写 PS 端 ddr 的数据，这里面涉及到 AXI4 协议，vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)
- 2021-01-22 17:46:44下载
- 积分：1
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AD
说明： FPGA控制AD7321的模块，是本人亲自试验过的。有Verilog源码，和简单文档。(FPGA control module of the AD7321 is personally tested. There Verilog source code, and simple document.)
- 2009-08-18 20:31:53下载
- 积分：1
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fft变换三个中的一个（站长：三个代码算一个）
fft变换三个中的一个（站长：三个代码算一个）-one of the three fft transfermation code
- 2022-02-10 13:45:18下载
- 积分：1
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TheResearchAndIPDesignOfSMBusBasedSmartBattery
本文研究了SMBus
规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下
(Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台
完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有
良好的性能。(This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.)
- 2009-03-26 12:16:53下载
- 积分：1
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encoding-decoding
卷积码编码译码程序以及其modelsim仿真波形文件等(Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file)
- 2020-12-27 20:59:03下载
- 积分：1
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16*16点阵显示”北京欢迎"
提供2个VHDL程序实现键盘显示的功能，第一个是16*16点阵显示“北京欢迎”，用VHDL语言编程实现，串烧在单片机实验工具箱上，让单片机点阵键盘上依次显示“北京欢迎”的字样。另附有LED数码管循环显示0～9数字的VHDL程序 ，成功串烧后，键盘上连续显示0~9这10个数字。
- 2022-08-03 09:36:55下载
- 积分：1
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利用正点院子开拓者fpga实现DDS功能
说明： 利用正点院子开拓者fpga实现DDS功能，实现三角波、正弦波、方波的发生。(Implementation of DDS with FPGA)
- 2019-08-21 09:30:18下载
- 积分：1
