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Verilog投币式手机充电仪
清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger
EDA major homework of digital electronic technology foundation course, Tsinghua University. Just put on the digital tube completely extinguished, press the start button, the digital tube display is 0. Enter a certain amount, the digital tube shows the amount of double the corresponding time, according to the confirmation began countdown. The maximum amount of input is 20. If there is no button in 10 seconds, the digital tube will die out.)
- 2020-12-10 16:29:20下载
- 积分：1
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ADC_Data_Recv_Module
接收机测试输入信号，
生成正余弦波，采样率、频率、幅度、相位可调节
并将生成的数据进行输出
压缩包包括Verilog代码、testbench代码、word文档
matlab仿真代码(The receiver tests the input signal,
Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted
And output the generated data
The compressed package includes the Verilog code, the testbench code
Matlab simulation code)
- 2017-12-08 17:56:02下载
- 积分：1
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74-Hamming-code-encoder-and-decoder
基于VHDL实现（7，4）汉明码的编码器和译码器(VHDL-based implementation (7,4) Hamming code encoder and decoder)
- 2011-06-09 20:47:07下载
- 积分：1
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FPGA实现LC12S无线通讯模块收发
FPGA实现LC12S无线通讯模块收发，使用Verilog语言。程序实现一个模块根据案件发送数据，另一个模块接受导数据后点亮LED灯。程序在XC3S500E上实现。
- 2022-01-26 03:51:50下载
- 积分：1
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实现串口传输代码
这是一个很好用的实现PC机与FPGA之间的数据传输
- 2022-03-24 04:05:35下载
- 积分：1
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mul24x24
24位x24位的乘法器
十分详细24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器(24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplication Explorer 24-bit x24 multiplier 24-bit x24-bit multiplier)
- 2009-06-08 10:00:58下载
- 积分：1
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sobel
由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
- 2021-01-15 21:08:46下载
- 积分：1
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cpu mips
实现多周期mips
设计一个32位MIPS多周期微处理器 具有多种 算数指令：
(Design a 32-bit MIPS microprocessor multi-cycle arithmetic instructions
- 2023-03-29 18:05:04下载
- 积分：1
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AHB-answers
这个文档回答了很多关于AHB总线在使用上经常遇到的问题(this doc gives a lot of answers for using AHB bus when doing design)
- 2020-10-21 12:17:24下载
- 积分：1
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FFT
64-point FFT/IFFT processor
architecture : Rrdix-SDF
- 2013-01-13 06:29:57下载
- 积分：1
