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MIPS_LANG
verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分：1
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系统设计
说明： 基于数码管独立显示和三色灯的交通指示系统设计(Design of Traffic Indicator System Based on Digital Tube Independent Display and Tri-color Lamp)
- 2020-06-21 02:00:01下载
- 积分：1
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通过实例的VHDL程序设计
VHDL programming by example
- 2022-03-19 05:46:52下载
- 积分：1
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22WALSH
1、掌握WALSH码产生的原理和WALSH码的特性。
2、掌握WALSH码的产生和特性分析的软件仿真。
3、掌握WALSH码的硬件产生方法。
(1, master code WALSH WALSH code generation principles and characteristics. 2, master WALSH code generation and characterization of the software simulation. 3, master code WALSH hardware generation approach.)
- 2020-07-03 08:40:01下载
- 积分：1
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802-11-Frame_E_C
Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a
station in Power Save mode
- 2016-08-23 17:37:40下载
- 积分：1
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基于fpga的fskpsk信号产生器，可实现对1.2kHz和2.4kHz正弦波的采样...
基于fpga的fskpsk信号产生器，可实现对1.2kHz和2.4kHz正弦波的采样-based on the fpga and fskpsk signal generator,can achieve sample to the 1.2kHz and 2.4kHz sin wave
- 2023-08-25 08:15:03下载
- 积分：1
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systolic
脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systolic）的乘法器(Pulse Multiplier: a GF (2m) domain on the Digit-Serial pulsation structure (Systolic) the multiplier)
- 2020-11-13 10:39:43下载
- 积分：1
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bootstrap_ace_v1.3.2
多年项目经验测试文档测试文档，重要保存重要保存重要保存重要保存重要保存重要保存(Years of project experience testing document testing, it is important to save save save important important important important to save save save important)
- 2016-03-05 15:46:27下载
- 积分：1
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8051IP nuclear source code
8051IP 核源代码-8051IP nuclear source code
- 2022-05-17 06:21:49下载
- 积分：1
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8位CPU的VHDL设计代码没有测试
8 bit cpu vhdl design code not tested
- 2022-03-21 20:07:37下载
- 积分：1
