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design-of-CAN-based-on-VHDL
基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性(Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness)
- 2011-07-22 15:22:27下载
- 积分：1
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ad73311
AD73311芯片的控制和数据程序，用于控制音频AD芯片。(AD73311 chip control and data program)
- 2021-02-01 23:20:00下载
- 积分：1
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SERDES_handbook
SERDES资料，包括reliability_handbook,serdes_handbook,serdes_introduction(SERDES doc,include reliability_handbook,serdes_handbook,serdes_introduction)
- 2017-01-12 18:28:41下载
- 积分：1
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FPGA_PSK
说明： 可以实现2PSK的信号调制，已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)
- 2019-05-09 16:29:17下载
- 积分：1
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Quartusrs232
串口通讯，与硬件联通调试过，收发程序是分开的。(Serial Communication)
- 2009-05-04 14:53:06下载
- 积分：1
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tdm_latest[1]
TDM，就是时分复用。本程序完成4通道，没通道最多32路64K信号的交换，就是说可以完成32x4个电话信号交换(TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange)
- 2010-07-07 15:28:06下载
- 积分：1
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这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子
这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting
- 2023-07-15 16:55:02下载
- 积分：1
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fault
fault minimization using genetic algorithm
- 2013-11-19 20:05:06下载
- 积分：1
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在 VHDL 中的离散余弦 Transform(DCT/IDCT)
项目目的是设计 DCT 和 IDCT 在 VHDL 中。离散余弦变换图像压缩中用于压缩的 JPEG 图像。此文件包含 DCT 和 IDCT 块和顶级模块于一体的两个块和矢量来测试这两个模块。
- 2022-02-05 11:13:18下载
- 积分：1
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dds_test
直接数字式频率合成器DDS设计、Verilog。
产生的信号可以是正弦波或方波、三角波、锯齿波等，自选。
采用DDS技术，将所需生成的波形写入ROM中，按照相位累加原理合成任意波形。
此方案得到的波形稳定，精度高，产生波形频率范围大，容易产生高频。
本实验在设计的模块中，包含以下功能：
（1）通过 freq 信号输入需要的频率的值；
（2）通过 wave_sel 信号选择所需的波形；
（3）通过 amp_adj 信号选择波形放大的倍数。(DDS design of direct digital frequency synthesizer, Verilog.
The generated signal can be sinusoidal or square wave, triangular wave, sawtooth wave and so on, optional.
By using DDS technology, the required waveforms are written into ROM, and arbitrary waveforms are synthesized according to the principle of phase accumulation.
The waveform obtained by this scheme is stable, accurate and easy to generate high frequency waveform.
This experiment includes the following functions in the designed module:
(1) Input the required frequency value through freq signal;
(2) Choosing the required waveform by wave_sel signal;
(3) Select the multiplier of waveform amplification by amp_adj signal.)
- 2019-01-19 16:07:50下载
- 积分：1
