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reed_solom
REEDSOLOMON source code
- 2010-04-30 17:44:52下载
- 积分：1
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A3P600-PQG208
Actel FPGA A3P600最小系统原理图，包含JTAG 、电源和封装 (Actel FPGA A3P600 minimum system schematics, including JTAG, power and packaging)
- 2012-12-03 11:29:19下载
- 积分：1
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Buzzer-music
基于FPGA实现蜂鸣器播放音乐的功能
使用芯片为EP2C8Q208C8N,使用普通蜂鸣器，由于频率不同可实现放歌功能，本例设计的是《友谊地久天长》，使用Verilog语言编程，本例子有工程文件、仿真、波形，经过测试可以使用。(Play music based on FPGA buzzer functions using chip EP2C8Q208C8N, using ordinary buzzer, since the frequency of different functions can be realized sing, in this case the design is " Auld Lang Syne" , using Verilog language programming, this project examples files, simulation, waveform, tested can be used.)
- 2016-07-05 16:15:13下载
- 积分：1
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wallace_multiplier
华莱士树乘法器，运用了华莱士树状结构和布斯算法，提高了速度(The Wallace tree multiplier uses the Wallace tree structure and the Buss algorithm to increase speed)
- 2020-12-26 10:29:03下载
- 积分：1
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Quartus a complete design examples, examples from installation to completion, th...
quartus一个完整的设计例子,从安装到实例完成，仿真等全过程，适合从0开始的初学者-Quartus a complete design examples, examples from installation to completion, the entire process of simulation, etc., suitable for the beginner to start from 0
- 2022-07-26 09:40:40下载
- 积分：1
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(15-7-2)BCH
Verilog HDL 语言编写的（15，7,2）BCH编码和译码功能(Verilog HDL language (15,7,2) BCH encoding and decoding functions)
- 2020-10-29 11:19:57下载
- 积分：1
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一个8位处理器结构，源码分析
说明： 关于一个8位处理器的分析，和源代码，VHDL语言设计，经过测试(on an eight processors, and source code, VHDL design, the test)
- 2005-12-27 21:39:45下载
- 积分：1
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bcd_to_dec
VHDL code for converting BCD to Decimal
- 2018-02-13 09:45:16下载
- 积分：1
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EDA应用中RAM具体定义实例，供大家学习和写程序参考之用
EDA应用中RAM具体定义实例，供大家学习和写程序参考之用-EDA applications, examples of the specific definition of RAM, for everyone to learn and write programs for reference
- 2022-08-18 02:44:17下载
- 积分：1
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标准电视信号的同步生成程序，利用VHDL和原理图，利用Quartus综合...
标准电视信号的同步生成程序，利用VHDL和原理图，利用Quartus综合-Standard television signal to generate the synchronization procedures, the use of VHDL and schematic diagram, using Quartus integrated
- 2022-03-13 05:08:34下载
- 积分：1
