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FPGA_实时时钟设计
通过配置DS1302芯片来实现实时时钟的监测,我们通过通过控制2个按键来选择我们要在数码管上显示的时间,按下按键1我们来显示周几,按下按键2来显示年月日,不按显示时分秒,这样显示复合我们的数字表的显示(By configuring DS1302 chip to monitor the real-time clock, we select the time that we want to display on the digital tube by controlling 2 keys. Press key 1 to show the week, press the key 2 to show the year and month, not according to the display time, so that the display of the display of the display of our digital table.)
- 2020-10-22 15:17:23下载
- 积分:1
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数字时钟
其一个数码时钟和闹钟,写在 verilog 的spartan 6,用户可以设置的帮助下电钮,伸直谴责的按钮实施,在正常操作中时钟滴答,然后控件来处理 Alaram 系统中,当 alaram 的时间匹配时钟原始时间的运行然后四个指示灯开始闪烁在该套件
- 2022-01-28 23:37:52下载
- 积分:1
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dgnszsz
多功能数字钟,在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)
- 2013-09-20 10:20:31下载
- 积分:1
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8 位 CPU vhdl实现(含全部源代码)
说明: 这是8位CPU的CVDL代码。CPU 的主要功能是执行指令,控制完成计算机的各项操作,包括运算操作、传送操作、输入/输出操作等。作为模型计算机设计,将重点放在寄存器级,采取较简单的组成模式,以尽量简洁的设计帮助学生掌握CPU 的基本原理。 此次设计CPU就是为了了解CPU运行的原理,从而完成从指令系统到CPU的设计,并且通过仿真对CPU设计进行正确性评定。(The main function of CPU is to execute instructions, control and complete various operations of computer, including operation, transfer operation, input / output operation, etc. As a model computer design, it focuses on register level and adopts a simpler composition mode to help students master the basic principles of CPU with a concise design as far as possible. This design of CPU is to understand the principle of CPU operation, so as to complete the design from instruction system to CPU, and evaluate the correctness of CPU design through simulation.)
- 2020-12-09 15:49:20下载
- 积分:1
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WM8731_WM8731L
wm8731音频编解码芯片使用介绍,该手册里面对该芯片进行了详细的描述,对各个单元模块也进行了详细的阐述(the handbook of WM8721/WM8731L)
- 2010-05-20 10:47:30下载
- 积分:1
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8_BUS
BUS documentation and map reffereces
- 2020-06-25 19:40:02下载
- 积分:1
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sim
调试bcm5396,写入和读取内部寄存器功能。功能验证可以用(Debug bcm5396, write and read the internal register function. Functional validation can be used)
- 2020-09-25 11:17:47下载
- 积分:1
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doc
说明: e200 riscv open code user guide
- 2020-06-15 22:45:01下载
- 积分:1
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RANGEN
2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码,verilog编写;包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)
- 2020-10-27 17:09:59下载
- 积分:1
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disparity
Disparity mapp code in VHDL
- 2017-11-30 14:48:59下载
- 积分:1