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fadd16
实验用16位全加器的VHDL代码,适合初学者学习,数电学习的好工具。
(Experiment with 16-bit full adder VHDL code for beginners to learn, a good tool to learn a few power.)
- 2010-05-11 20:37:34下载
- 积分:1
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fenpin
这是一个二进制的最简单分频器,是一个简短的fpga代码,用verilog书写(This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog)
- 2013-11-17 15:01:30下载
- 积分:1
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leading-zero
对于32位寄存器前导零个数的计数,一个简单的程序(32 registers a leading zero number of counts, a simple procedure)
- 2012-06-05 16:41:11下载
- 积分:1
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myTurbo_test
Turbo编码的FPGA实现,采用了(7,5)RSC编码和循环移位交织,帧长度128bit(The FPGA implementation of Turbo coding adopts (7, 5) RSC coding and cyclic shift interleaving, and the frame length is 128bit.)
- 2018-04-17 17:29:33下载
- 积分:1
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cordic_verilog
cordic算法的verilog 语言实现,注释详细,资料齐全,实现了cordic算法的各个功能,可以计算正余弦(cordic algorithm verilog language, detailed notes, and complete information)
- 2020-06-29 16:20:02下载
- 积分:1
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uart
UART功能,可以增加在NIOS2內,主要來做外部Flash的擦除及寫入,需搭配上位機傳輸字串來控制(UART function, can increase the NIOS2, the main external Flash to do the erase and write, to be a string with the host computer to control the transmission)
- 2011-08-25 09:32:35下载
- 积分:1
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UART
说明: 串口通信vivado实现,带有仿真文件,可实现数据收发(the uart program based on vivado)
- 2020-07-02 16:15:57下载
- 积分:1
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RS232协议Verilog实现
RS232协议的Verilog简单实现,包含发送和接收模块。
- 2023-04-18 18:15:03下载
- 积分:1
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vga
VGA显示控制:时序控制+像素点的颜色处理显示十字光标(vorilog)(VGA Display Control: Timing Control+ pixel color processing and display cross cursor (vorilog))
- 2010-11-27 14:02:12下载
- 积分:1
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32位D触发器
D触发器是最简单,最常用,最具代表性的时序元件,它是现代数字系统设计中最基本的底层时序单元,甚至是ASIC设计的标准单元。JK和T触发器都由D触发器构建而来。D触发器的描述包含了Verilog对时序电路的最基本和典型的表达方式,同时也包含了Verilog许多最具特色的语言现象。
- 2022-08-17 11:15:02下载
- 积分:1