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近几年关于高速Reed
近几年关于高速Reed-Solomon编译码实现的论文，详细讲述了Chein，Forney,解方程模块的设计-In recent years, the high-speed Reed-Solomon coding and decoding achieve the papers detail in Chein, Forney, solving equations Module
- 2022-04-26 16:50:33下载
- 积分：1
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实现Reed_Solomon码的快速解码的原理及其算法，帮助设计ＲＳ译码的硬件实现...
实现Reed_Solomon码的快速解码的原理及其算法，帮助设计ＲＳ译码的硬件实现-Code Reed_Solomon realize fast decoding principle and algorithm, designed to help realize the hardware decoding RS
- 2022-03-14 20:53:51下载
- 积分：1
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深化对资源应用的理解，以避免死锁的概念，…
加深了解有关资源申请、避免死锁等概念，并体会和了解死锁和避免死锁的具体实施方法。
要求编写和调试一个系统动态分配资源的简单模拟程序，观察死锁产生的条件，并采用银行家算法，有效的防止和避免死锁的发生。
-deepen understanding of the application of resources to avoid deadlock concepts, and share and understand the deadlock and avoid the deadlock specific implementation methods. Prepared and debugging a system dynamic allocation of resources simple simulation program to observe the conditions Deadlock, Banker algorithm used effectively to prevent and avoid the deadlock occurred.
- 2022-01-26 05:25:56下载
- 积分：1
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通用的系统权限设计功能,角色,用户,权限
角色,用户,权限
通用的系统权限设计功能,角色,用户,权限
角色,用户,权限-Universal design features of system privileges, roles, users, permissions to roles, users, permissions
- 2022-01-24 09:07:53下载
- 积分：1
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阳初s3c2440开发板的原理图
1.S3C2440_Kernel.pdf
2.S3C2440_Base.pdf
3.S3C2440_Base.op...
阳初s3c2440开发板的原理图
1.S3C2440_Kernel.pdf
2.S3C2440_Base.pdf
3.S3C2440_Base.opj
4.S3C2440_BASE.DSN-Yang early S3C2440 development board schematic diagram of 1.S3C2440_Kernel.pdf2.S3C2440_Base.pdf3.S3C2440_Base.opj4.S3C2440_BASE.DSN
- 2022-02-01 21:05:01下载
- 积分：1
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This article: FPGA method used to simulate the high dynamic (Global Position Sys...
本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。-This article: FPGA method used to simulate the high dynamic (Global Position System GPS) signal source of the C/A code generator. C/A code in GPS to achieve sub-sites, the satellite signal capture coarse and fine code (P code) lead capture plays an important role, through hardware description language Verilog in ISE to achieve circuit to generate, using MODELSIM, SYNPLIFY simulation tools were and integrated.
- 2022-02-05 10:44:00下载
- 积分：1
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VB开发的三层体系结构与数据库编程原理几示例
VB开发的三层体系结构与数据库编程原理几示例-VB development of the three-tier architecture and database programming principle several examples
- 2022-10-25 08:05:04下载
- 积分：1
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采用ARM和FPGA组合，共同实现电脑横机控制器
采用ARM和FPGA组合，共同实现电脑横机控制器-The use of ARM and FPGA combination of a common computerized flat knitting machine controller
- 2022-05-21 05:59:40下载
- 积分：1
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16位微处理器设计方案，计算机组成原理毕业设计
16位微处理器设计方案，计算机组成原理毕业设计-16-bit microprocessor design, computer design of the composition of the principle of graduation
- 2022-03-16 19:38:04下载
- 积分：1
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CH372 Driver Program,for reference only,test file
CH372 Driver Program,for reference only,test file
- 2022-01-26 07:32:36下载
- 积分：1
