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bianyuanjiance
说明： 图像采集 VGA输出 图像的边缘 ov7670(V image acquisition VGA output image edge)
- 2020-06-21 13:20:06下载
- 积分：1
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这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!...
这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!-This is my learning process in the middle of the 10-minute program, containing various clock module and the counter, accumulator, and can download, compile!
- 2022-07-19 00:32:21下载
- 积分：1
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《阿东+手把手教你学FPGA》完美公开版
一本很好的教程，适合初学者,里面有详细的教程，很值得一看！！(A good tutorial, suitable for beginners, there are detailed tutorials, it is worth a visit!!)
- 2018-06-20 19:41:52下载
- 积分：1
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110819_1
基于sopc的lcd时钟，开发工具为nios ii和quartus ii9.0(Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0)
- 2011-08-22 10:28:50下载
- 积分：1
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jesd204_0_ex
jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)
- 2020-11-26 14:49:31下载
- 积分：1
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ethernet_tri_mode_rtl.tar
以太网控制器verilog，含有mac,mii接口(Ethernet controller verilog, containing mac, mii interface)
- 2007-12-19 23:51:08下载
- 积分：1
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updown
VHDL Programmes -2 for dumping on FPGA
- 2014-02-12 00:22:46下载
- 积分：1
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FIR滤波器的基本Verilog代码实现
FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
- 2023-05-26 13:40:03下载
- 积分：1
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generate-coordinates
使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。(Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm.)
- 2013-08-28 11:03:46下载
- 积分：1
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Verilog keyboard input program for led lights display
verilog 键盘输入程序，用于led灯的显示-Verilog keyboard input program for led lights display
- 2023-01-08 14:55:03下载
- 积分：1
