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performance with rayleigh
说明: matlab bpsk with rayleigh performance expirement
- 2020-06-24 21:40:01下载
- 积分:1
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TIMING LEARNING
TIMING LEARNING -TIMING LEARNING
- 2023-04-26 09:15:03下载
- 积分:1
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electronic-lock-and-VHDL-design
基于Max+Plus II和VHDL的电子密码锁设计(Based on Max+ Plus II electronic lock and VHDL design)
- 2011-11-17 10:19:40下载
- 积分:1
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gundong
说明: 通过按键输入学号,并循环显示:
电路功能描述:通过Ego1上的按键输入自己的学号(8位10进制数),并存储在32位的寄存器中;8位10进制数输入完成后,实现滚动显示效果。(Enter the student number by pressing the key, and display it in a cycle:
Circuit function description: input one's own student number (8-digit decimal number) through the key on ego1, and store it in 32-bit register; after the completion of 8-digit decimal number input, the scrolling display effect is realized.)
- 2020-12-19 16:09:10下载
- 积分:1
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TDMsystem
实现多路可变时分复用,包括复接器,解复接,比特同步,帧同步,分频器(Implement multi-channel variable time division multiplexing, including multiplexer, demultiplexing, bit synchronization, frame synchronization, frequency divider)
- 2018-09-16 23:29:09下载
- 积分:1
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verilog写的数字频率计的显示模块,可以
verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be
- 2022-03-23 18:10:33下载
- 积分:1
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VHDL描述的自定义交织器
交织器主要是对输入数据按照一定的规则打乱以便减少数据中过长的连0或者连1的出现。交织矩阵为行列矩阵,msgin为输入比特,msgout为交织输出比特,row和rol为交织器的行和列,可以通过改变col改变交织深度。先把输入的比特流数据改变为一个矩阵,再按照一定的方式输出为比特流数据
- 2022-03-15 22:36:53下载
- 积分:1
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这是用verilog硬件描述语言编的5分频代码
这是用verilog硬件描述语言编的5分频代码-This is verilog hardware description language code is compiled by five divider
- 2023-05-11 18:05:04下载
- 积分:1
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AGC
使用FPGA完成AGC 自动增益的代码,适合初学者(FPGA to complete the use of AGC automatic gain code, suitable for beginners)
- 2020-12-28 16:09:01下载
- 积分:1
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VHDL语言的cookbook,能够使你更快的学会使用VHdL
VHDL语言的cookbook,能够使你更快的学会使用VHdL-cookbook
- 2022-01-26 00:47:39下载
- 积分:1