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VHDL Digital Full ADDER Logic Program
- 2022-08-03 08:35:11下载
- 积分:1
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Read_SPI_ADC
This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.
- 2015-10-13 14:43:13下载
- 积分:1
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test-ram
design ram v8051 for project
- 2013-07-08 23:24:20下载
- 积分:1
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VGA
VHDL语言实现VGA的显示彩条横条九宫格的功能。(VGA display color of the VHDL language bar Jiugongge function.)
- 2013-05-07 10:04:10下载
- 积分:1
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VHDL实用教程(潘松),非常经典讲解VHDL语言,包含基本语法及实例。...
VHDL实用教程(潘松),非常经典讲解VHDL语言,包含基本语法及实例。-VHDL Practical Guide (Pan Song), is a classic on the VHDL language, including basic grammar and examples.
- 2022-08-07 10:44:16下载
- 积分:1
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rs_encoder
RS编码器的fpga实现,有TESTBench(RS encoder to achieve the fpga, and TESTBench)
- 2009-06-24 11:37:04下载
- 积分:1
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VHDL language used to write the VGA control procedures have been verified, the a...
用VHDL语言写的VGA 控制程序,已经验证过,绝对好用!-VHDL language used to write the VGA control procedures have been verified, the absolute ease of use!
- 2022-01-23 11:20:28下载
- 积分:1
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利用VHDL语言设计一个分频器,输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024...
利用VHDL语言设计一个分频器,输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024-The use of VHDL language design a divider, input CLK, the output respectively, CLK1, CLK8, CLK256, CLK1024
- 2022-06-02 16:58:00下载
- 积分:1
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循环码的verilog编码程序
(7,4)循环码的verilog编码程序,(7,4)循环码的verilog译码程序((7,4) cyclic code Verilog coding procedures, (7,4) cyclic code the verilog decoding procedure)
- 2020-06-27 02:00:02下载
- 积分:1
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zedboard
xilinx的zed板详细开发资料,对初学者和开发人员都有帮助(The Xilinx zed board detailed development information, helpful for beginners and developers)
- 2013-04-22 16:44:31下载
- 积分:1