-
DC-Voltmeter
Use this multimeter to make precise electronic measurements and tests. Easy-to-read LCD readout, positive set selector switch and 32" leads. AC voltage
- 2013-01-07 22:52:54下载
- 积分:1
-
使用VHDL实现三角函数的计算
为了便于计算结果在FPGA中后续的计算和ip核中的调用,本代码输入信号为普通浮点型数据,输出为32位表示的浮点型数据。
- 2022-07-21 05:59:31下载
- 积分:1
-
VHDL_modelling_guidelines是vhdl建模开发的指导资料
VHDL_modelling_guidelines是vhdl建模开发的指导资料-VHDL modeling VHDL_modelling_guidelines is guiding the development of information
- 2022-03-12 23:37:10下载
- 积分:1
-
sine_cordic
generate sine wave. Inputs : Amplitude, phasein, frequency
- 2013-07-22 10:25:41下载
- 积分:1
-
fffffff
如上图所示, Rst是低电平有效的系统复位信号,Clk是时钟信号。AB[5:0]是地址信号,DB[7:0]是数据信号,wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后,可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后,给出一个Clk周期宽度的脉冲信号start,则系统从存储器0地址处开始读出数据,读出的8位数据从低位开始以3位为一组,每个时钟周期输出一组,即第一个时钟周期输出[2:0]位,第二个时钟周期输出[5:3]位,第三个周期输出1地址的[0]位和0地址的[7:6]位,直至将存储器中64x8数据全部输出。若最后一组不足三位,则高位补0。
(As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2020-11-04 20:39:51下载
- 积分:1
-
DDR SDRAM控制器的VHDL代码
DDR SDRAM控制器的VHDL代码已经测试-DDR SDRAM controller VHDL code
- 2022-02-24 20:41:05下载
- 积分:1
-
OFDM-system-FPGA-design
说明: OFDM基带处理的书籍和论文,以及发送和接收端源码。(OFDM baseband processing books and papers, as well as send and receive source code.)
- 2020-06-06 13:54:22下载
- 积分:1
-
VHDL描述的自定义交织器
交织器主要是对输入数据按照一定的规则打乱以便减少数据中过长的连0或者连1的出现。交织矩阵为行列矩阵,msgin为输入比特,msgout为交织输出比特,row和rol为交织器的行和列,可以通过改变col改变交织深度。先把输入的比特流数据改变为一个矩阵,再按照一定的方式输出为比特流数据
- 2022-03-15 22:36:53下载
- 积分:1
-
Huffman
用VHDL编写的huffman编码的源程序(With the VHDL source code written in huffman coding)
- 2010-06-08 14:58:32下载
- 积分:1
-
FPGA_OV5640_VGA_DDR3_code
说明: 基于OV5640摄像头的视频图像传输存储以及读取。供大家参考。(Video image transmission, storage and reading based on ov5640 camera. For your reference.)
- 2021-03-06 15:39:30下载
- 积分:1