登录
首页 » Verilog » aynchronous fifo 项目

aynchronous fifo 项目

于 2022-04-30 发布 文件大小:12.52 MB
0 46
下载积分: 2 下载次数: 1

代码说明:

先入先出 (FIFO) 内存结构广泛用于缓冲处理块之间的数据传输。高性能、 高复杂度数字系统越来越多地被要求不同的模块之间传输数据,甚至不相关的时钟频率。双时钟 FIFO 是一个更复杂的函数,可提供高速数据缓冲对于异步时钟域应用程序。建议的设计利用了一种有效的内存数组结构,并可以运行在应用程序中存在多个时钟周期的延迟时间的地方。它还包括一个可配置的同步电路,同步异步信号 FIFO 内。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • altfp_matrix_mult
    浮点数 矩阵乘法模块 verilog语言编写 可直接调用(Floating-point matrix multiplication module can directly call verilog language)
    2013-12-18 15:08:36下载
    积分:1
  • cm03pr2
    In computer storage, multipath I/O is a fault-tolerance and performance enhancement technique whereby there is more than one physical path between the CPU in a computer system and its mass storage devices through the buses, controllers, switches, and bridge devices connecting them
    2013-06-09 00:41:09下载
    积分:1
  • wide_cbf
    宽带波束形成,设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz,对白噪声序列进行滤波,即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)
    2013-03-19 09:40:45下载
    积分:1
  • DE2_70_Control_Panel_v1.3.0
    DE2-70开发板中附带的控制面板,可以读取存储器中的数据,这个可以正常连接和读取,有好几版本的,有的不能用,而这个经过我亲自测试。(DE2-70 development board comes with a control panel, you can read the data in the memory, this can be properly connected and read, there are several versions, and some can not be used, and this after I personally tested.)
    2012-10-06 22:29:11下载
    积分:1
  • 简单的键盘接口模块程序
    一个简单的键盘接口模块程序,对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)
    2020-06-24 02:00:02下载
    积分:1
  • FPGA
    spwm dcac逆变 fpga与单片机一起作用(sdad)
    2010-08-12 18:20:08下载
    积分:1
  • turbo_encoder
    在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。(Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.)
    2021-04-19 09:38:51下载
    积分:1
  • PID controller verilog源代码
    The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first calculates the error between a measured value (PV) and its ideal value (SP), then use the error as an argument to calculate the manipulate value(MV). The MV will adjust the process to minimize the error. It can be used to calculate duty cycle for PWM (Pulse Width Modulation).
    2022-09-23 12:05:03下载
    积分:1
  • FPGA_DSP_Rapid-IO
    基于FPGA实现DSP与Rapid-IO网络互联()
    2017-10-31 09:53:20下载
    积分:1
  • i2c_master_bfm仿真模型
    i2c_master_bfm,可以直接使用实现i2c master的仿真功能
    2023-08-23 13:05:03下载
    积分:1
  • 696518资源总数
  • 104297会员总数
  • 29今日下载