登录
首页 » VHDL » i2c bus project implementation can be used in altera verification environment

i2c bus project implementation can be used in altera verification environment

于 2022-04-29 发布 文件大小:74.45 kB
0 48
下载积分: 2 下载次数: 1

代码说明:

i2c总线的工程实现,可以用在altera环境下验证-i2c bus project implementation can be used in altera verification environment

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • HYG32024032T-bT62L-VA
    此为华远显示320*240LCD驱动程序,该程序也适用于带RA8806控制器的LCD(This is the Huayuan display 320* 240LCD driver, the program also applies with RA8806 LCD controller)
    2013-06-08 16:12:53下载
    积分:1
  • Traffice LED Controller base on FSM
    Traffice LED Controller base on FSM 1. for crossroad, each road with 3 led: green, red, yellow. 2. only use one counter.
    2022-09-04 13:15:02下载
    积分:1
  • fen pin qi
    半整数分频器的实现(verilog),本文以6.5分频为例!很实用的!-fen pin qi
    2022-02-01 02:05:40下载
    积分:1
  • aulap3_IsadoraStangarlin
    Code developed in classroom
    2017-09-28 00:51:06下载
    积分:1
  • Booth Algorithm Based Squarer Design
    设计一个8位有符号数字平方器。平方器将接收操作数B,一个8位有符号数。新兴市场;
    2022-04-06 14:59:44下载
    积分:1
  • rs232_3
    说明:  为串口收发器以及汉明编码,将电脑通过串口发送的7位数据转化成汉明码显示于led上,或把接收到的11位汉明码解码并验错纠错(For the serial port transceiver, and Hamming codes, the computer through the serial port into 7-bit data displayed on the led on the Hamming code, or to receive the 11 Hamming code error correction decoding and experience)
    2010-04-29 22:18:02下载
    积分:1
  • 此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块,一个提供同步信号(H_SYNC和V_SYNC)及像素位置信息;...
    此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块,一个提供同步信号(H_SYNC和V_SYNC)及像素位置信息;另一个接收像素位置信息,并输出颜色信号。这样便于进行图形修改,同时也容易实现- This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature modules the entire electric circuit, provides the synchronized signal (H_SYNC and V_SYNC) and the picture element positional information; Another receive picture element positional information, and output color signal. Like this is advantageous for carries on the graph to revise, simultaneously is also easy to realize
    2022-04-07 13:58:38下载
    积分:1
  • QMD
    实现了QPSK的调制,使用了ise自带的dds的IP核(QPSK is modulated and the IP core of DDS is used in ise.)
    2019-05-05 15:37:58下载
    积分:1
  • sram_test
    is61lv25616简单的verilog程序,完成sram读写(is61lv25616 simple verilog program, complete sram read and write)
    2013-07-18 11:16:50下载
    积分:1
  • 合众大公司XILINX_V4实验箱原理图
    合众大公司XILINX_V4实验箱原理图-United XILINX_V4 large companies schematic experimental box
    2022-12-12 08:15:03下载
    积分:1
  • 696518资源总数
  • 104313会员总数
  • 30今日下载