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StopWatch
This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
- 2013-10-04 00:53:49下载
- 积分:1
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I2C的VHDL源码,从机模式,编译通过。
I2C的VHDL源码,从机模式,编译通过。-I2C the VHDL source code, from the mode, the compiler through.
- 2023-01-11 08:00:03下载
- 积分:1
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1_Carm
说明: 经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)
- 2019-03-19 13:38:29下载
- 积分:1
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BLDC_Simplorer_Maxwell_Cosimulation
这个是永磁无刷直流电机的本体结构和控制电路的联合仿真,既可以设计电机的结构,又可以搭电机的控制系统。(This is the body structure of the permanent magnet brushless DC motor and control circuit co-simulation, both the structure of the motor can be designed, they can take control of the motor system.)
- 2021-03-26 11:39:13下载
- 积分:1
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基本的 VHDL 程序
基本的VHDL程序本rar文件。 请点击左侧文件开始预览 !预览只提供20%的代码片段,完整代码需下载后查看 加载中 侵权举报
- 2022-05-24 21:08:13下载
- 积分:1
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verilog写的数字频率计的显示模块,可以
verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be
- 2022-03-23 18:10:33下载
- 积分:1
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codings
wavelet transform of a signal,it is important and useful code to trans form frequency to time domain
- 2013-11-10 15:10:32下载
- 积分:1
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function_automatic
Verilog使用automatic function的範例(Verilog example of the use of the automatic function)
- 2009-06-18 12:01:30下载
- 积分:1
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Verilog HDL数字设计与综合 夏宇闻译(第二版)
电子书籍 verilog HDL 数字设计与综合 夏宇闻所编写(electronic text
Foreign electronic and communication textbooks)
- 2021-01-15 15:18:45下载
- 积分:1
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VHDL-Code-For-Full-Adder-By-Data-Flow-Modelling
VHDL Code For Full Adder By Data Flow Modelling
- 2013-11-08 00:39:04下载
- 积分:1