登录
首页 » VHDL » Divider can be very good VHDL divider realize the function of great help for beg...

Divider can be very good VHDL divider realize the function of great help for beg...

于 2022-04-21 发布 文件大小:1.12 kB
0 62
下载积分: 2 下载次数: 1

代码说明:

除法器,可以很好的实现VHDL除法器的功能对于初学者有很大帮助. -Divider can be very good VHDL divider realize the function of great help for beginners.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • maichongceliang
    对于已获得的脉冲包络采样序列,需测量的脉冲特征参数主要有:脉冲幅值(PA)、脉冲到达时间(TOA)和脉冲宽度(PW)。实际测量中,脉冲波形的形状是各种各样的,但其主要的参数有脉冲幅度、脉冲宽度、脉冲周期、脉冲占空比、脉冲前沿(上升时间)、脉冲后沿(下降时间)、脉冲上冲、脉冲下冲、脉冲下垂、脉冲顶部不平度等,脉冲参数的计量主要就是对这些参数进行计量。本程序包实现基于FPGA实现脉冲宽度和重复周期的测量。(Who have access to the pulse envelope sample sequence, the pulse measurement to be the main characteristic parameters are: pulse amplitude (PA), pulse time of arrival (TOA) and pulse width (PW). The actual measurement, the pulse shape is a wide variety of shapes, but its main parameters of the pulse amplitude, pulse width, pulse period, pulse duty cycle, pulse leading edge (rise time), pulse along (down time), the red pulse, pulse undershoot, pulse droop, pulse irregularities, such as at the top, the measurement of pulse parameters is mainly the measurement of these parameters. The package FPGA-based pulse width and repetition to achieve the measurement cycle.)
    2009-07-08 14:32:08下载
    积分:1
  • UART_RX_
    fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)
    2020-06-18 04:00:01下载
    积分:1
  • gtx
    ip core of the transceiver gtx
    2019-04-02 00:10:03下载
    积分:1
  • jtag
    verilog jtag源码及原理,还有debug模块。边界扫描等(verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.)
    2021-04-27 14:18:44下载
    积分:1
  • rc6 加密
    此代码是加密实现在 vhdl。在加密、 RC6 (Rivest Cipher 6) 是一种对称密钥 块密码从RC5派生。它是由Ron Rivest、马特 Robshaw、 雷西德尼和益群丽莎贤以满足高级加密标准(AES)竞争的要求设计的。该算法是一个五个入围者,和也提交给湖怪兽和CRYPTREC项目。它是一种专有
    2023-04-17 09:45:04下载
    积分:1
  • 随机数发生器
    随机数发生器
    2023-04-30 09:25:03下载
    积分:1
  • SMBus
    SMbus通讯协议的Verilog程序段,已通过Moldesim的仿真,可用(Verilog program segment of the SMbus communication protocol, has been through the Moldesim simulation, the available)
    2021-03-24 18:29:15下载
    积分:1
  • tdc
    线性伸展TDC的verilog,包含门级网表(TDC linear stretch of verilog, includes gate-level netlist)
    2021-01-04 18:58:55下载
    积分:1
  • 10_ImageEdge
    基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)
    2020-10-23 20:27:22下载
    积分:1
  • or1200.tar
    OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders
    2014-12-20 04:40:23下载
    积分:1
  • 696518资源总数
  • 104305会员总数
  • 11今日下载