-
用Matlab编写fft
在MATLAB下自编实现快速傅里叶分析，(Fast fft own procedures, faster than the system call fft slowe)
- 2020-06-23 09:00:02下载
- 积分：1
-
vhdl 键盘程序，对键盘输入的字符进行判断，写入fpga中
vhdl 键盘程序，对键盘输入的字符进行判断，写入fpga中-VHDL key
- 2022-03-03 15:13:57下载
- 积分：1
-
1
说明： 一个解决除法溢出的例子，可以学习到很多，注释很详细(A solution to the division overflow example, you can learn a lot, very detailed notes)
- 2013-12-24 09:19:13下载
- 积分：1
-
VHDL实现led灯的动态扫描，主要对CLK进行分频
VHDL实现led灯的动态扫描，主要对CLK进行分频-VHDL realization led lamp dynamic scan, the main points of the CLK to the frequency
- 2023-03-21 08:35:04下载
- 积分：1
-
dl.sh
linux cmd line download script
- 2012-03-15 02:51:11下载
- 积分：1
-
32_lvds_test
说明： Xilinx 公司Spartan-6系列FPGA实现LVDS，带Modelsim仿真文件，已综合。(Xilinx Spartan-6 Series FPGA implements LVDS with Modelsim simulation file, which has been synthesized.)
- 2020-11-30 20:59:27下载
- 积分：1
-
vga_core
Code VHDL for control VGA
FPGA: Xilinx, Altera
- 2012-09-09 10:54:28下载
- 积分：1
-
使用从Digilent Spartan3E板VGA接口。LabVIEW VI
VGA interface using Spartan3E board from DIGILENT.Labview .vi
- 2023-02-15 00:10:04下载
- 积分：1
-
ise
xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能(Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance)
- 2007-09-20 14:30:52下载
- 积分：1
-
bundle_test5
说明： 一个具备bp协议典型功能的数据传输系统（超时重传机制以及托管传输）包含五个节点(A data transmission system with typical functions of BP protocol (Overtime retransmission mechanism and managed transmission) consists of five nodes)
- 2019-12-02 19:06:44下载
- 积分：1
