-
unishift
An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.
- 2009-09-24 18:56:48下载
- 积分：1
-
vhdl
vhdl code for internet interface
- 2014-12-04 04:58:04下载
- 积分：1
-
VHDL ip core的设计，软核的设计方法
VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design
- 2022-06-01 06:05:02下载
- 积分：1
-
source
说明： altera fpga 实现fft，用fft IP核，有matlab仿真代码(Altera FPGA implementation of FFT, FFT IP core, matlab simulation code)
- 2020-12-18 20:29:11下载
- 积分：1
-
VHDL语言描述的二进制十进制译码电路，已经编译完成
VHDL语言描述的二进制十进制译码电路，已经编译完成-Binary decimal decoder circuit
- 2022-02-22 00:13:01下载
- 积分：1
-
通过vga通讯控制显示器显示七彩条文，通过quartus编译的程序，可用...
通过vga通讯控制显示器显示七彩条文，通过quartus编译的程序，可用-Communication and Control through the vga display colorful provisions quartus compiled through the procedures that can be used
- 2022-01-22 17:41:13下载
- 积分：1
-
20190718
uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device
- 2020-06-21 21:40:01下载
- 积分：1
-
rscode
RS编码器在fpga上的实现，用的modelsim开发环境(RS encoder in the realization of the fpga, development environment used in modelsim)
- 2009-06-11 21:45:49下载
- 积分：1
-
LCD1602测试程序
实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)
- 2020-06-23 21:00:01下载
- 积分：1
-
usb2lpt
German REAL LPT! USB2LPT
- 2012-08-05 03:33:40下载
- 积分：1
