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JIAOTONGDENG
用VERILOG实现 交通灯控制，且运行正确，希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)
- 2014-01-05 20:38:03下载
- 积分：1
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RS232RefComp
本文档介绍了通用异步收发器（UART）VHDL 组件，它可以使用，也可以与PmodRS232或与一个板上的RS232端口。一个UART 部件被用于转换串行数据为并行数据，并且并行数据为串行数据。串行 转移到UART数据被放置在一个输出总线经过了UART将其转换成并行 信息。该总线可以被用作输入到其它逻辑门阵列中。所得到的数据可 然后再次使用UART组件被送回了串行。
- 2022-05-13 15:17:28下载
- 积分：1
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利用VHDL语言设计一个分频器，输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024...
利用VHDL语言设计一个分频器，输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024-The use of VHDL language design a divider, input CLK, the output respectively, CLK1, CLK8, CLK256, CLK1024
- 2022-06-02 16:58:00下载
- 积分：1
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基于VHDL语言的解码汉明编码，其中包含子
基于VHDL语言的汉明码的译码，含有校正子跟纠错检错功能-Based on the VHDL language decoding Hamming Code, which contains sub-calibration error with error correction function
- 2022-08-11 19:51:06下载
- 积分：1
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Three
Three-input Majority Voter
-- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.
-Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.
- 2022-08-12 06:51:37下载
- 积分：1
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48_4.12
网络通信中的MII接口
通常将4位nibble数据送出，此程序将4位数据组合成8位数据并行输出（8比特==1个字节）。。完全可用
同时包含84转换(The MII network interface usually sent four nibble data, this procedure will be 4-bit data into 8-bit parallel output data (8 bits == 1 byte). . Completely available at the same time contains 84 conversion)
- 2009-04-21 13:43:45下载
- 积分：1
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maichongceliang
对于已获得的脉冲包络采样序列，需测量的脉冲特征参数主要有：脉冲幅值(PA)、脉冲到达时间(TOA)和脉冲宽度(PW)。实际测量中，脉冲波形的形状是各种各样的，但其主要的参数有脉冲幅度、脉冲宽度、脉冲周期、脉冲占空比、脉冲前沿(上升时间)、脉冲后沿(下降时间)、脉冲上冲、脉冲下冲、脉冲下垂、脉冲顶部不平度等，脉冲参数的计量主要就是对这些参数进行计量。本程序包实现基于FPGA实现脉冲宽度和重复周期的测量。(Who have access to the pulse envelope sample sequence, the pulse measurement to be the main characteristic parameters are: pulse amplitude (PA), pulse time of arrival (TOA) and pulse width (PW). The actual measurement, the pulse shape is a wide variety of shapes, but its main parameters of the pulse amplitude, pulse width, pulse period, pulse duty cycle, pulse leading edge (rise time), pulse along (down time), the red pulse, pulse undershoot, pulse droop, pulse irregularities, such as at the top, the measurement of pulse parameters is mainly the measurement of these parameters. The package FPGA-based pulse width and repetition to achieve the measurement cycle.)
- 2009-07-08 14:32:08下载
- 积分：1
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基于EPM1270的PS2键盘鼠标驱动源码Verilog
基于EPM1270的PS2键盘鼠标驱动源码Verilog-Based on the EPM1270 the PS2 keyboard and mouse-driven Verilog source
- 2023-04-28 06:25:04下载
- 积分：1
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用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench
用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
- 2022-01-27 08:43:52下载
- 积分：1
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利用扫描加记数程序实现百进制,适合VHDL的初学者使用.
利用扫描加记数程序实现百进制,适合VHDL的初学者使用.-increase in the use of scanning program in mind several hundred 229 and is suitable for beginners to use VHDL.
- 2022-03-21 06:59:03下载
- 积分：1
