-
8b10b Verilog
8bit/10bit编码Verilog实现(8bit/10bit Verilog Code)
- 2018-09-18 10:29:44下载
- 积分：1
-
CC
说明： 802.16d 的卷积编码和解码的VHDL实现(802.16d cc encoding and decoding,writing in VHDL)
- 2015-05-14 23:05:54下载
- 积分：1
-
VHDL在SOURCEINSIGHT的插件
VHDL在SOURCEINSIGHT的插件-VHDL in SOURCEINSIGHT plug-ins
- 2022-08-13 02:07:02下载
- 积分：1
-
本文提供了一个CMOS控制器，使Nios II可以利用C.
本文提供了一种CMOS控制器，使Nios-II可以利用CMOS控制器控制CMOS，并允许在CMOS图像上传送SDRAM。在DE2-70平台上运行
- 2022-02-12 08:29:38下载
- 积分：1
-
Double_Pulse_Test
利用VHDL语言描述出一个双脉冲，可任意设置两脉冲长和中间时间间隔。(A double pulse is described in VHDL language, and the two pulse length and the intermediate time interval can be arbitrarily set.)
- 2020-11-22 12:29:35下载
- 积分：1
-
乘法器,实现了乘法和除法的功能,能够进行32位的运算
乘法器,实现了乘法和除法的功能,能够进行32位的运算-Multiplier to achieve the functions of multiplication and division to carry out 32-bit computing
- 2022-03-24 02:44:07下载
- 积分：1
-
SimpleVOut-master
SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals
in various formats. The cores connect using AXI-streams. Most configurations
(resolution, framerate, colordepth, etc.) are set at compile-time using
Verilog parameters. See svo_defines.vh for details on those parameters.
- 2020-06-24 21:20:01下载
- 积分：1
-
wide_cbf
宽带波束形成，设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz，对白噪声序列进行滤波，即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)
- 2013-03-19 09:40:45下载
- 积分：1
-
ASYNC_FIFO_SYNTH
This file contains async fifo design
- 2014-03-01 20:48:22下载
- 积分：1
-
How to Connecting Xilinx FPGAs to the Philips
How to Connecting Xilinx FPGAs to the Philips
- 2022-08-14 17:50:57下载
- 积分：1
