-
HDB3
用Verilog HDL语言进行HDB3编码，并通过Quartus Ⅱ仿真验证(With the Verilog HDL language HDB3 coding, and simulation by Quartus Ⅱ)
- 2020-11-30 11:19:28下载
- 积分：1
-
基于EPM1270的PS2键盘鼠标驱动源码Verilog
基于EPM1270的PS2键盘鼠标驱动源码Verilog-Based on the EPM1270 the PS2 keyboard and mouse-driven Verilog source
- 2023-04-28 06:25:04下载
- 积分：1
-
LDPC_DVB-T2
LDPC encoding code in 1/2code rate for DVB-T2
- 2014-03-11 08:05:18下载
- 积分：1
-
xapp953
Two-Dimensional Rank Order Filter
Author: Gabor Szedo
- 2012-05-15 02:50:41下载
- 积分：1
-
traffic_lights
交通灯控制器控制红（r）、绿（g）、黄（y）三种不同颜色的交通灯，这三种不同颜色灯的亮、灭分别由三个定时器（timer1、timer2、timer3）控制；
当某个定时器工作时，它所控制的交通灯亮，直到设定的定时时间到（该定时器状态由’0’变’1’），交通灯跳转到另一种状态；
clk是脉冲控制端（图中未标出）；reset是异步复位端，复位状态为红色交通灯亮；
输出端r、g、y分别表示三种颜色交通灯的亮、灭状态。
( traffic light controller control red (R), green (g), yellow (y) three different colors of traffic lights, three different colors of bright lights, off by three timer (Timer1, Timer2, Timer3 ) control When a timer work, it controls the traffic lights, until the set timing (the timer status ' 0 ' for ' 1' ), traffic lights Jump to another state clk is the pulse control terminal (not shown) reset is asynchronous reset terminal, the reset state for the red traffic lights output terminal r, g, y represent the three colors of traffic lights bright, the off state.)
- 2020-12-19 15:09:10下载
- 积分：1
-
Cirrus Logic EP9302 原理图 ORCAD格式
Cirrus Logic EP9302 原理图 ORCAD格式-Cirrus Logic EP9302 schematic ORCAD format
- 2022-08-22 05:47:43下载
- 积分：1
-
AMI1
本代码是用VERILOG语言描述的AMI码的解码的程序，经过调试是正确的。代码简单易懂。(This code is described in VERILOG language AMI code decoding process, after debugging is correct. Code is easy to understand.)
- 2021-04-22 14:48:48下载
- 积分：1
-
AXI-HP-PDMAPGIC
本文参考了Xilinx 官方文档UG873，“System Design Using Processing System High
Performance Slave Port”。主要实现了PL 中AXI CDMA IP 与PS 部分HP64bit 从接口集成。
本例中AXI CDMA 部分扮演主机，从PS 部分DDR 系统内存中源缓冲区拷贝一列数据到目
的缓冲区。可以分别采用裸机工程和基于Linux 的应用软件来实现功能。(This reference to the official document Xilinx UG873, " System Design Using Processing System High Performance Slave Port" . The main achievement of the PL in AXI CDMA IP interface integration with PS part HP64bit. In this example AXI CDMA part to play host, a copy of a column of data into the destination buffer section PS source DDR system memory buffer. Can respectively bare engineering and Linux-based applications to achieve functional.)
- 2014-12-23 10:27:24下载
- 积分：1
-
psk_rician-channel-MATLAB
QPSK在赖斯信道下的模拟仿真，包括K=6和K=10下的情况(QPSK in, Laisi Xin Road, under the simulation, including the case of K = 6 and K = 10 under)
- 2013-04-26 21:30:18下载
- 积分：1
-
DE2_115_TV
DE2-115开发板TV摄像头成像程序，源码亲测可用，可加入边缘算法成像，实时显示轮廓，速度流畅(The DE2-115 development board TV camera imaging procedures, the pro-test in the source can be added to the edge algorithms imaging, real-time display contours, fast-paced)
- 2020-07-09 19:18:55下载
- 积分：1
