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digital-system-design
基于VHDL语言的七段显示管程序, 实现9个数字循环 并且能控制播放速度(SEVEN SEGMENT DISPLAY)
- 2011-02-14 21:02:38下载
- 积分:1
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步进电机
此代码是用于旋转一个步进电机所需的方向。
- 2022-10-22 10:05:04下载
- 积分:1
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JTAG design verilog code.
JTAG design verilog code.
- 2022-02-14 02:08:42下载
- 积分:1
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File name: ADC0809.vhd features: Based on the VHDL language, easy to control imp...
文件名:ADC0809.vhd功能:基于VHDL语言,实现对ADC0809简单控制说明:ADC0809没有内部时钟,需外接10KHz~1290Hz的时钟号,这里由FPGA的系统时钟(50MHz)经256分频得到clk1(195KHz)作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.
- 2023-07-04 18:20:03下载
- 积分:1
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vhdl实现的鼠标协议,代码可读性高,适合作为参考案例。
vhdl实现的鼠标协议,代码可读性高,适合作为参考案例。-VHDL realize mouse agreement, the code readable, suitable as a reference case.
- 2022-02-06 08:18:06下载
- 积分:1
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claa
vhdl code for carry lookahead addder
- 2014-02-05 00:26:26下载
- 积分:1
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EnDat
ENDAT 协议说明,包括时序等详细的说明,(endat Encoder characteristics)
- 2021-05-12 22:30:02下载
- 积分:1
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Quadrature Deshifrator
这个
- 2022-06-29 04:52:15下载
- 积分:1
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V2.tar
SDIO slave, written in verilog, does not support SPI mode.
- 2021-04-05 16:59:04下载
- 积分:1
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ba_ker
巴克码装到信息内同时将巴克码识别出来,实现帧同步的VHDL设计(Barker code loaded to the information identified while Barker code, VHDL design to achieve frame synchronization)
- 2014-05-18 17:37:39下载
- 积分:1