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divisor
Time divisor vhdl code
- 2009-06-02 21:31:05下载
- 积分：1
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FPGA DDS
使用DE2实现DDS，步骤简单，配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)
- 2020-06-23 10:00:01下载
- 积分：1
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tb_time_offfset
说明： offset_cancellation code for matlab to hdl
- 2020-06-17 12:20:02下载
- 积分：1
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DE2_115_Synthesizer
FPGA implementation of simple Multi-tone Electronic Keyboard using DE2-115 board with a PS/2 keyboard and speaker
- 2013-08-20 19:48:32下载
- 积分：1
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sync_bitops
Set a bit and return its old value.
- 2015-06-23 14:22:31下载
- 积分：1
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wirebus总线nand flash controller
wirebus总线nand flash controller，基础入门控制器，内存管理，fpga实现。已编译通过。编译平台quartus ii
- 2023-02-28 07:40:03下载
- 积分：1
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performance-of-pcie
本白皮书探讨了在PCI Express的因素
技术可能会影响性能。它还
提供指导如何估算
的系统性能。(This white paper explores the factors in PCI Express technology may affect performance. It also provides guidance on how to estimate the system performance.)
- 2013-10-29 10:52:43下载
- 积分：1
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MAX2769配置源码_配置参数经过实际工程考验
对常用的射频端下变频的MAX2769芯片进行GPSL1频点配置，实测有效，该配置参数是经过实际工程验证的，现在也应用于实际项目中
- 2023-09-04 07:35:03下载
- 积分：1
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usbd_ucos
基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)
- 2020-09-09 09:38:02下载
- 积分：1
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ad9467_config1
说明： 采用Verilog编写AD9467配置文件(Using Verilog to write ad9467 configuration file)
- 2020-07-03 15:40:02下载
- 积分：1
