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Add_sub_struc
8位加减器,八位减法器与加法器,用过一个控制端可以自由变换,采用移位加法方式,用途广泛,利用减法位补码加法的理论实现。(8 addition and subtraction, eight subtractor and adder, used a control terminal can freely change the using Shift addition, a wide range of uses, the use of subtraction complement addition theory to achieve.)
- 2012-05-14 20:36:26下载
- 积分:1
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小灯测试代码
使用Verilog语言编写小灯测试代码,能实现流水灯的功能,代码简单易懂,很适合初学者学习和验证。
- 2022-02-28 22:00:42下载
- 积分:1
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VHDL-the-count
利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发
时钟,计数器进行加计数,并利用数码管进行显示,当计数到9999 时,从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger
The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count
)
- 2012-01-13 14:01:38下载
- 积分:1
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29_ad9226_test
本实验将采用双通道 12bit AD 9226在开发板上实现数据采集和模数
转换的功能(This experiment will use dual channel 12bit AD 9226 to realize data acquisition and module on the development board.
The function of conversion)
- 2020-12-06 21:09:21下载
- 积分:1
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sdram_cmd命令集
sdram_cmd.v是控制sdram的命令集合。网上资料,是控制sdram的命令集合。网上资料。控制sdram的命令集合。网上资料控制sdram的命令集合。网上资料。
- 2022-05-10 21:41:40下载
- 积分:1
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raised-cosine-filter
代码实现了一个根升余弦成型滤波器,2PAM信号通过此成型滤波器,并且匹配接收,画出了发送和接收波形,验证了代码的正确性。(The code designs a root raised cosine filter,2PAM signal transmitted through the filter and matched using the same filter, I plot the transmitted signal and received signal to verify the correctness of the code.)
- 2012-11-09 21:59:53下载
- 积分:1
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halfband
verilog写的39阶通带为20KHz的半带fir滤波器,经测试正确。(verilog halfband FIR)
- 2020-12-25 14:29:04下载
- 积分:1
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arbiter_ip
Arbiter code for simulation purpose
- 2013-07-13 17:45:11下载
- 积分:1
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Cordic实现Sin Cos, Verilog
verilog语言实现的cordic算法,计算sin cos三角函数
- 2023-06-11 16:25:04下载
- 积分:1
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CH372
USB设备接口的驱动程序,采用verilogHDL语言编写,并包含相关说明资料(USB device driver interface, using verilogHDL language, and contains descriptive information)
- 2014-01-03 02:23:08下载
- 积分:1