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a file server, accessed via the web, is the network version ATLDraw
一个文档服务器程序，通过网页访问，是ATLDraw的网络版本-a file server, accessed via the web, is the network version ATLDraw
- 2023-05-27 07:25:03下载
- 积分：1
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Lua 是一个扩展式程序设计语言，它被设计成支持通用的过程式编程，并有相关数据描述的设施。 Lua 也能对面向对象编程，函数式编程，数据驱动式编程提供很好的支持...
Lua 是一个扩展式程序设计语言，它被设计成支持通用的过程式编程，并有相关数据描述的设施。 Lua 也能对面向对象编程，函数式编程，数据驱动式编程提供很好的支持。它可以作为一个强大、轻量的脚本语言，供任何需要的程序使用。 Lua 以一个用 clean C 写成的库形式提供。（所谓 Clean C ，指的 ANSI C 和 C++ 中共通的一个子集）-Lua is an extension of programming language, it is designed to support the process of general-purpose programming, and have the relevant data description facilities. Lua can also object-oriented programming, functional programming, data-driven programming to provide good support. It could serve as a strong, light-weight scripting language for the use of any necessary procedures. Using Lua with a clean C library written in the form. (The so-called Clean C, refers to ANSI C and C++ CPC
- 2022-01-25 19:28:29下载
- 积分：1
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CY7C68013 eeprom images
C Y7C68013 eeprom images
CY7C68013 eeprom images
CY7C68013 eeprom images
C Y7C68013 eeprom images
CY7C68013 eeprom images
- 2023-08-10 01:40:03下载
- 积分：1
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见过最好的css手册，功能内容之完整度令人窒息。
见过最好的css手册，功能内容之完整度令人窒息。-Seen the best css manuals, content-integrity features suffocating.
- 2022-08-15 06:41:56下载
- 积分：1
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C语言实力 看你C语言的能力以及翻译的能力
C语言实力 看你C语言的能力以及翻译的能力-C-strength, the ability to see your C language and translation capacity
- 2023-05-25 16:20:03下载
- 积分：1
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Sip protocol structure throuth a sample
Sip protocol structure throuth a sample
- 2022-03-13 16:57:34下载
- 积分：1
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borland c++chengxujiac，it is very valuable for c++ builder programmers.if you ha...
borland c++chengxujiac，it is very valuable for c++ builder programmers.if you have any problems, you can write to me.-borland c chengxujiac. it is very valuable for c builder programmers.i f you have any problems, you can write to me.
- 2022-03-25 04:20:15下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
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symbian development
symbian development
- 2023-06-02 21:20:03下载
- 积分：1
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Another book on VLSI
Another book on VLSI
- 2023-04-30 09:30:09下载
- 积分：1
