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daima
Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。
(Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2014-12-11 20:16:04下载
- 积分：1
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DE2_CCD_sobel
通过摄像头图像的提取，在FPGA开发板上实现的，主要实现了图像轮廓的提取(Extraction of the image through the camera, in the FPGA implementation of the development board, the main achievement of the image contour extraction)
- 2020-07-22 17:48:45下载
- 积分：1
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分数阶傅里叶变换FRFT的土耳其算法的FPGA实现的程序 FRFT Ozaktas
这是分数阶傅里叶变换FRFT的土耳其算法的FPGA实现的程序，FPGA是Xilinx的virtecx-5，这是我在做毕业设计的时候自己编写的，希望能对你有帮助！(This is the fractional Fourier transform algorithm FRFT Turkish FPGA implementation of the program, FPGA is the Xilinx virtecx-5, which is what I was doing graduate design time I have written, I hope you can help!)
- 2021-03-12 10:49:25下载
- 积分：1
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Get-20-point
this program get 20 point from user and draw functions.
- 2014-01-09 03:25:06下载
- 积分：1
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svpwm3
说明： 基於空間向量調變的開關法，在於載波做比較切出方波再送至開關讓馬達啟動(Based on the switching method of space vector modulation, the square wave is cut out for carrier comparison and sent to the switch to start the moto)
- 2019-01-04 16:07:37下载
- 积分：1
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codes
EKG SIGNAL PROCESSING THROUGH CORDIC
- 2013-09-29 01:46:17下载
- 积分：1
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Verilog数字系统设计教程(第二版) 夏宇闻
说明： Verilog数字系统设计教程(第二版) 夏宇闻(Verilog Digital System Design Course (2nd Edition) Xia Yuwen)
- 2020-06-20 18:40:02下载
- 积分：1
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sdram verilog
sdram FPGA verilog设计 有源码有设计文档
- 2023-04-21 03:40:04下载
- 积分：1
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TW2867_ADV7171
FPGA TW2867输入到ADV7171显示实验(FPGA TW2867 input to the ADV7171 display experiment)
- 2021-03-19 15:19:19下载
- 积分：1
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spi_interface
说明： spi通用串行总线，4线控制，可读写操作(SPI universal serial bus, 4-wire control, readable and writable operation)
- 2019-04-29 12:37:55下载
- 积分：1
