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EDA-Cont-LED-201006
FPGA-CPLD实习计数器7段数码管控制接口设计与LED显示控制，FPGA译码(FPGA-CPLD internship counter 7-segment LED control interface design and LED display control, FPGA decoder)
- 2013-05-11 23:09:25下载
- 积分：1
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ml50x_schematics
xilinx公司的virtex-5开发板原理图 需要的可以下载看一下 希望对你有帮助(xilinx company virtex-5 development board schematics can download look you want to help)
- 2012-09-12 08:49:31下载
- 积分：1
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AHB2APB Bridge 的Verilog
在AMBA bus 总线中，AHB是高速的总线接口，APB则是低速的总线接口，有些低速的外设不需要接入高速的外设时，便通过桥接的方式接入APB总线中。
- 2022-01-20 22:42:04下载
- 积分：1
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fffffff
如上图所示， Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。
(As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2020-11-04 20:39:51下载
- 积分：1
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Uart_Analysis
rs422通信，此模块实现通信功能，使用Verilog语言(RS422 communication program, Verilog language, this module implements 422 communication function.)
- 2021-03-23 16:29:15下载
- 积分：1
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C51tou-wen-jian
是51单片机常用头文件定义，直接调用就可以，包括：1602液晶，12864液晶，5110屏，I2C,UART,精确延时函数，PWM调速，DS1302，DS18B20,,,,,,,(51 microcontroller used header file defines direct call can include: 1602 LCD, 12864 LCD, 5110 screen, I2C, UART, precision delay function PWM speed control, DS1302, DS18B20,,,,,)
- 2013-04-15 17:34:22下载
- 积分：1
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ug_dsp_builder
本文是Altera公司编写的dspbuilder的设计方法，但是是英文原版的(This article is prepared by Altera Corporation dspbuilder design method, but it is the original English edition of)
- 2008-12-14 01:33:58下载
- 积分：1
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CodedLOCK
基于FPGA的电子密码锁设计与实现，语言是VHDL语言，有注释(FPGA-based design and implementation of electronic locks, language is VHDL language, annotated)
- 2013-08-27 21:37:06下载
- 积分：1
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i2c的systemverilog vip，功能齐备，架构简洁
i2c的systemverilog vip，功能齐备，架构简洁她是用SystemVerilog写的验证模型，支持master和slave模式，支持stop bit和start bit的产生
- 2022-07-06 10:34:50下载
- 积分：1
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apb-uart
apb—uart模块，实现中断处理和异步收发数据并处理(APB - UART module, interrupting processing and asynchronous receiving and receiving data and processing)
- 2020-11-06 14:19:52下载
- 积分：1
