-
adder_array
adder_array的设计。加法器阵列设计,顶层模块,四步流水,21位(adder_array the design. The adder array design, top-level module, four-step pipeline, 21)
- 2013-04-17 00:19:05下载
- 积分:1
-
8_sys_clock
黑金开发板对时钟信号的编写实验以及调试,相关代码如压缩包所示(CLOCK FPGA)
- 2012-09-18 22:51:36下载
- 积分:1
-
RS
通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)
- 2021-04-28 15:48:44下载
- 积分:1
-
amba3-vip-master
说明: All AMBA bus protocols - AXI3, AXI4, AXI4-Lite, ACE, AHB
- 2021-01-11 10:08:49下载
- 积分:1
-
ISE_uart
自己在ISE下用VHDL写的UART,简单,易懂(in ISE using VHDL was the UART, simple, understandable)
- 2021-03-08 21:59:28下载
- 积分:1
-
rs_enc
Verilog code for RS-(255,239) encoder.
- 2021-04-06 16:19:02下载
- 积分:1
-
dianzhen(ok)
驱动8*8点阵块显示汉字,可以自己根据要显示的内容随意更改,已通过验证。(Blocks of 8* 8 dot matrix drive display Chinese characters, you can display the content according to their random changes, has been verified.)
- 2010-12-28 16:42:07下载
- 积分:1
-
READ_SINEX
读取IGS数据中心提供的sinex文件 并恢复法方程(Read sinex file IGS data centers and to restore normal equation)
- 2016-06-18 11:19:14下载
- 积分:1
-
DMA_controller
dma传输控制程序,Verilog编写,通过编译,完全可用
- 2022-09-18 05:20:03下载
- 积分:1
-
VGA
VGA彩条信号显示控制电路设计,能通过vga显示横条纹竖条纹棋盘条纹(VGA color signal display control circuit design)
- 2017-12-07 20:55:10下载
- 积分:1