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new
1、PC和寄存器组使用时钟触发。
2、指令存储器和数据存储器存储单元宽度一律使用8位，即一个字节的存储单位。
3、控制器部分可以考虑用控制信号真值表方法（有共性部分）与用case语句方法逐个产生各指令其它控制信号相配合，注意：信号必须与状态配合。。当然，还可以用其它方法，自己考虑。
4、试用的汇编程序，而且必须包含所要求的所有指令。Slt、sltu指令必须检查两种情况：“小于”和“大于等于”；beq、bne指令必须检查两种情况：“等”和“不等”。这段汇编程序必须尽量优化，同时，给出每条指令在内存中的地址。(1, PC and register groups are clocked.
2, the command memory and data memory storage unit width will use 8 bits, that is, a byte storage unit.
3, the controller part can be considered with the control signal truth table method (common part) and with the case statement method to produce each command other control signal match, Note: the signal must be with the state. The Of course, you can also use other methods to consider their own.
4, try the assembler, and must contain all the required instructions. Slt, sltu instruction must check two cases: "less than" and "greater than or equal to"; beq, bne instruction must check two cases: "wait" and "unequal". This assembler must be optimized as much as possible, giving the address of each instruction in memory.)
- 2017-10-19 09:44:13下载
- 积分：1
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ads4449_config
说明： 配置ADS4449,SPI接口；中文说明不能小于20字(Configure ads4449,Chinese description cannot be less than 20 words)
- 2020-11-30 16:19:27下载
- 积分：1
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uartverilog
说明： 实现FPGA多字节的稳定串口通信，改编自特权同学的FPGA代码(Realize the stable serial communication of multi-byte FPGA and adapt the FPGA code from Quan via Quartus by Verilog)
- 2020-11-16 08:39:40下载
- 积分：1
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FPGASPI
FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)
- 2020-12-09 13:49:20下载
- 积分：1
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BPSK
说明： 八相移键控调制的Verilog程序，给出了各个子模块的程序，实现了信号调制。(Eight-phase shift keying modulation of the Verilog program, each module is given the procedures, the signal modulation.)
- 2011-02-24 13:15:15下载
- 积分：1
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v5_emac
以太网的FPGA程序实现以太网的FPGA程序实现以太网的FPGA程序实现(enternet verilog fpga)
- 2013-12-15 23:08:11下载
- 积分：1
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DC-Voltmeter
Use this multimeter to make precise electronic measurements and tests. Easy-to-read LCD readout, positive set selector switch and 32" leads. AC voltage
- 2013-01-07 22:52:54下载
- 积分：1
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基于FPGA的fir滤波器的代码
用verilog 语言写的一个fir低通滤波器的程序，原始数据通过matlab来输入，输出给matlab来显示结果
- 2023-01-22 04:40:07下载
- 积分：1
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flash
本程序是fpga控制flash的读写程序，包括了程序和仿真时的测试文件(fpga flash)
- 2013-07-21 14:47:36下载
- 积分：1
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FPGA-SRAM_Test
利用FPGA实现SDRAM的读写操作，通过硬件测试。(FPGA implementation using SDRAM to read and write operation, hardware testing.)
- 2011-08-03 22:52:25下载
- 积分：1
