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walsh
沃尔什函数发生器工程文件，Quartus Ⅱ 13.0版本(Walsh Function Generator)
- 2020-07-03 08:20:01下载
- 积分：1
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RS编解码的FPGA实现
RS（255,239） FEC , 编解码， FPGA， 《RS编解码的FPGA实现》， 东南大学硕士论文用到的源代码，以及详细讲解-RS（上传 (上传 (1)1)255,239）， FEC， encoding and decoding, postgraduate s essay
- 2022-04-20 16:01:16下载
- 积分：1
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amba3-vip-master
说明： All AMBA bus protocols - AXI3, AXI4, AXI4-Lite, ACE, AHB
- 2021-01-11 10:08:49下载
- 积分：1
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cordic
实现可连续输入数据做三角函数变换处理，通过verilog代码实现，(It realizes triangular function transformation for continuous input data.)
- 2020-06-21 22:40:01下载
- 积分：1
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SPI
design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
- 2010-08-17 19:16:12下载
- 积分：1
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verilog三阶数字锁相环
输入信号为bpsk信号，载波中频为5Mhz，多普勒为10k，接收机三阶锁相环实现对bpsk调制信号的载波进行复制和跟踪,
- 2023-01-30 05:45:03下载
- 积分：1
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AD9516VERILOG
通过VERILOG编写的AD9516时钟芯片SPI配置代码(CONGIGURE THE ad9516)
- 2021-03-15 12:09:23下载
- 积分：1
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XAPP134_SDRAM_VHDL
XAPP134 SDRAM VHDL design file
- 2011-01-19 09:57:21下载
- 积分：1
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altera-de2-ann
基于VHDL+FPGA的神经网络设计，实现简单的字符识别(Design of Neural Network Based on VHDL+FPGA to Realize Simple Character Recognition)
- 2018-12-01 08:06:02下载
- 积分：1
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Verilog_HDLjiaocheng
Verilog HDL教程
什么是Verilog HDL？
Verilog HDL 硬件描述语言(What is a Verilog HDL tutorials Verilog HDL? Verilog HDL hardware description language)
- 2009-06-15 21:44:11下载
- 积分：1
