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ds312_Spartan-3E-FPGA
FPGA资料与所用元器件的数据参考手册与应用指南(ds312_Spartan-3E FPGA Family )
- 2012-09-18 21:43:54下载
- 积分：1
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project_1
说明： 简单的一个Verilog小程序，适合刚接触的人群(A simple Verilog small program, suitable for people just contact)
- 2020-06-16 22:20:01下载
- 积分：1
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Verilog_HDLjiaocheng
Verilog HDL教程
什么是Verilog HDL？
Verilog HDL 硬件描述语言(What is a Verilog HDL tutorials Verilog HDL? Verilog HDL hardware description language)
- 2009-06-15 21:44:11下载
- 积分：1
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实战训练21 SDRAM硬件控制
说明： SDRAM硬件控制,fpga的verilog语言，适合学习(SDRAM hardware control, Verilog language of FPGA, suitable for learning)
- 2020-04-29 11:45:16下载
- 积分：1
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FPGA
数字钟的VHDL语言程序，包含了好几个模块，是毕业设计的优秀程序，值得下载！(VHDL language program of digital clock, contains several modules, is an excellent program, graduation design is worth to download!)
- 2015-08-31 21:07:44下载
- 积分：1
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uart_test
说明： 用于实现上位机与下位机之间通过RS232协议来进行通讯。(It is used to realize communication between upper computer and lower computer through RS232 protocol.)
- 2019-03-13 14:15:24下载
- 积分：1
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实光电码盘的输出数据的四倍频，使码盘输出精度提高四倍。...
实光电码盘的输出数据的四倍频，使码盘输出精度提高四倍。-real photoelectric encoder output data of the four frequency, accuracy encoder output increased by four times.
- 2022-01-23 10:41:40下载
- 积分：1
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sram_test_OK
主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动，SRAM型号为IS61LV25616，程序语言为Verilog,开发环境为quartusII 7.0,为一工程，可直接下载到FPGA中，含电路图(Mainly based on FPGA (EP2C8Q208I8) driving under the SRAM, SRAM model IS61LV25616, programming language for Verilog, a development environment for quartusII 7.0, for a project, can be downloaded directly to the FPGA, including circuit diagrams)
- 2014-12-24 22:08:36下载
- 积分：1
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Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, en...
基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal
- 2022-03-17 02:46:02下载
- 积分：1
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RS
说明： 本文设计了基于FPGA的，用verilog HDL语言描述的在伽罗华域GF（ ）上的RS（6,4）编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述，然后在软件上进行编译、仿真，最终实现RS（6,4）编码，下载之后用chipscope采集数据，分析符合仿真结果，达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS (6,4) encoder. Using the ISE software Verilog HDL language for each module is described, and then compile, simulation in software, the ultimate realization of the RS (6,4) encoding, after downloading by chipscope data acquisition, the analysis with the simulation results meet the design requirements.)
- 2017-08-25 17:59:14下载
- 积分：1
