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BISS
说明: biss协议源码交流 verilog hdl源码,测试可用(Biss protocol ,achieved by verilog HDL,can be verify using modelsim or other simtools.)
- 2020-12-02 09:19:26下载
- 积分:1
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手把手教你学FPGA 语法篇
编程规范是重中之重,带你书写良好的变成习惯(It is used to measure noise and detect road noise pollution. It is accurate and has good effect.)
- 2018-03-10 20:49:51下载
- 积分:1
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SDRAM
基于fpga与verilog语言的的sdram读写(SDRAM reading and writing based on FPGA and Verilog language)
- 2018-01-16 11:24:03下载
- 积分:1
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decode
用Verilog实现汉明码编码,经测试可正确使用,代码简洁(Verilog with Hamming code encoding, the test can be used correctly, the code is simple)
- 2017-03-10 19:28:21下载
- 积分:1
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即使
偶数分频,包括验证程序,verilog实现,可综合-Even-numbered sub-frequency, including the verification process, verilog realize, can be integrated
- 2022-04-22 19:15:58下载
- 积分:1
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用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench
用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
- 2022-01-27 08:43:52下载
- 积分:1
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cpri
基于verilog的cpri接口代码,支持各种速率自由切换,量产产品实际应用代码(Cpri interface based on verilog code, support various rate free switch, production products the actual application code)
- 2015-09-21 16:59:59下载
- 积分:1
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DDS-Waveform-generator
采用FPGA实现的DDS波形发生器源码,可以实现频率幅值变换、正弦波、方波、三角波输出,输出频率可达1MHz(FPGA implementation of the DDS waveform generator source frequency amplitude transform, sine wave, square wave, triangle wave output, the output frequency up to 1MHz)
- 2012-06-29 23:20:58下载
- 积分:1
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atom.2007.12.tar
Cores are generated from Confluence a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C
- 2008-05-12 10:13:23下载
- 积分:1
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Study the performance of state machine. Rar inspect the performance of state mac...
状态机的性能考察.rar
状态机的性能考察.rar-Study the performance of state machine. Rar inspect the performance of state machine. Rar
- 2023-04-13 19:15:04下载
- 积分:1