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uart_zhiwen
RS232的UART编程，包括波特率发生器模块，串口接受模块，串口发送模块(RS232 programming the UART, including the baud rate generator module, serial module to receive, send serial module)
- 2009-04-10 10:57:05下载
- 积分：1
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这是一个verilog代码为根升余弦滤波器
this is a verilog code for root raised cosine filter
- 2022-05-25 01:29:30下载
- 积分：1
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UART
实现了UART的底层协议，加入了控制器，其波特率可以根据使用进行调整；发送模块、接收模块相互独立，互不影响。(Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.)
- 2013-11-30 13:25:21下载
- 积分：1
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VHDL digital system design and engineering practice 4, including the principles,...
VHDL数字系统设计和工程实践5，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice 4, including the principles, truth table and schematic, as well as VHDL source code.
- 2022-08-11 13:48:51下载
- 积分：1
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VHDL
控制电话信令
完成忙碌 等待 回铃音振铃等(Signaling complete control over telephone ring so busy waiting ringback tone)
- 2010-10-22 20:11:38下载
- 积分：1
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ALU用VHDL项目
ALU using VHDL project
- 2022-03-22 23:35:27下载
- 积分：1
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CJ2
关键词：清华大学计算机系 计算机组成原理大实验 多周期cpu工程源码，内含中断，串口，以及31个指令的实现，读写内存，控制器，ALU，寄存器，分频等模块，小作业什么的可以直接从里面摘抄，为学弟学妹造福(Keywords: Department of Computer Science Computer Composition Principle experimental multi-cycle the cpu Engineering source for the benefit of mentees)
- 2020-12-29 10:09:01下载
- 积分：1
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generateCAcode
gps C/A码生成
生成gps32颗卫星伪码，方便，经过测试(gps C/A code generation to generate pseudo-code satellites gps32, convenient and tested)
- 2021-05-13 04:30:02下载
- 积分：1
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Tempe_deteV2.1
说明： FPGA接收串口UART发来的指令设定温度报警值，实时采集DS18B20温度传感器并显示，带报警功能(FPGA receives the instruction from UART, sets the temperature alarm value, collects and displays DS18B20 temperature sensor in real time, with alarm function)
- 2021-04-13 13:28:56下载
- 积分：1
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33753129vhdl
对数计算源程序，能够在FPGA中计算某数的对数(Determined on the basis of the source, calculated in the FPGA to a certain number of log)
- 2009-06-17 19:41:57下载
- 积分：1
