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俄罗斯方块（Xilinx版）
说明： 用verilog语言开发俄罗斯方块小游戏(Developing Tetris game with Verilog language)
- 2020-11-27 08:47:38下载
- 积分：1
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FFT_VHDl
VHDL实现快速傅里叶变换，内附带资料以及源代码。(VHDL fast Fourier transform, within the supplied data and source code.)
- 2020-08-14 20:08:27下载
- 积分：1
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mul_ser12
本源码是用Verilog编写的12位移位相加乘法器的设计源码，开发软件为MAX+PLUS，已经测试通过。(The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.)
- 2011-05-31 14:19:30下载
- 积分：1
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YCbCr444_YCbCr422
FPGA YCbCr444转YCbCr422实验 很好的参考(FPGA EP4CE40F23C6 YCbCr444 turn YCbCr422 experiment)
- 2021-01-25 10:08:38下载
- 积分：1
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Baseband_line_code
基于VHDL语言的基带线路码产生电路设计（毕业论文），内涵完整的源代码(Based on VHDL language baseband line code generation circuit design (Thesis), meaning the complete source code)
- 2010-07-03 22:38:09下载
- 积分：1
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dividefrequency
如何用VHDL语言对时钟进行分频以达到计数目的(how to achive counting by VHDL Language)
- 2009-02-13 15:45:38下载
- 积分：1
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cordic implementation in vhdl&c
cordic implementation in vhdl&c
- 2022-10-31 01:55:03下载
- 积分：1
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CH4CH2CH1VHDL 数字电路参考书所有程序9
CH4CH2CH1VHDL 数字电路参考书所有程序9-CH4CH2CH1VHDL digital circuit reference all proceedings 9
- 2022-11-24 11:15:04下载
- 积分：1
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sync-and-asyn_FIFO_verilog
同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)
- 2021-03-07 14:19:29下载
- 积分：1
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联邦滤波法lianbanglvbo
联邦滤波法，毕设时写的，可以和其他方法的做比较(Kalman filter, write the complete set up, and other methods to compare)
- 2020-12-01 18:49:26下载
- 积分：1
