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vc senior programming skills! ! Further understanding vc
vc高级编程的一些技巧！！可以进一步理解vc-vc senior programming skills! ! Further understanding vc
- 2022-01-22 15:09:24下载
- 积分：1
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mfc深入浅出（第二版）第二部分
mfc深入浅出（第二版）第二部分-mfc easy (second edition) Part 2
- 2023-07-05 11:55:03下载
- 积分：1
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铰接式NFS根文件系统，Linux使用
挂接NFS为根文件系统的方法,linux下使用-articulated NFS root file system, Linux use
- 2022-04-12 21:00:01下载
- 积分：1
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此书重点介绍了java游戏的编写方法，不仅对于初学者，而且对于java程序员都是一个很好的借鉴教材...
此书重点介绍了java游戏的编写方法，不仅对于初学者，而且对于java程序员都是一个很好的借鉴教材-This book focus on introducing the way of programming java games. Not only it benefits the new to java, but also it is a useful teaching material to programmers
- 2022-05-16 05:00:52下载
- 积分：1
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分形源程序集合,很有价值! 国外代码!
分形源程序集合,很有价值! 国外代码!-Fractal source pool of great value! Foreign code!
- 2022-05-23 05:04:36下载
- 积分：1
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蚁群优化作者简介：Marco Dorigo和克日什托夫S.
《An Introduction to Ant Colony Optimization》
作者：Marco Dorigo and Krzysztof Socha
时间：Technical Report No.TR/IRIDIA/2006-010April 2006
一份介绍蚁群系统的英文原版论文报告- An Introduction to Ant Colony Optimization Author: Marco Dorigo and Krzysztof Socha time: Technical Report No.TR/IRIDIA/2006-010April 2006 Colony introduce a system of paper reporting the original English edition
- 2022-02-07 21:45:54下载
- 积分：1
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VBScript language reference
VBScript语言参考-VBScript language reference
- 2022-03-28 21:26:42下载
- 积分：1
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一本关于软件开发配置管理的书，还是不错的，介绍了一些有关协同开发的东西。值得一看...
一本关于软件开发配置管理的书，还是不错的，介绍了一些有关协同开发的东西。值得一看-one of configuration management software development, the book is still good, some of the Cooperative Development of things. An eye-catcher
- 2022-06-12 18:46:42下载
- 积分：1
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Sliding mode control
Sliding mode control
- 2022-10-17 21:35:03下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
