登录
首页 » VHDL » USB+FPGA电路设计原理图,实际的电路板运行正常,很有参考意义。...

USB+FPGA电路设计原理图,实际的电路板运行正常,很有参考意义。...

于 2022-02-06 发布 文件大小:35.89 kB
0 159
下载积分: 2 下载次数: 1

代码说明:

USB+FPGA电路设计原理图,实际的电路板运行正常,很有参考意义。-usb_sch

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • fjq1
    介绍了在数字语音通信中, 利用在系统可编程技术和复杂可编程逻辑器件CPLD, 实现了数字语音的复接和分接 对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。实际应用结果表明, 系统工作稳 定可靠, 设计是成功的。(Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic device CPLD, to achieve the digital voice multiplexer and demultiplexer for the single steady state in which the digital circuit and digital phase locked loop extraction bit synchronization signals are also carried out a detailed design specification. The practical application results show that the system works stable and reliable design is successful.)
    2020-12-01 10:39:28下载
    积分:1
  • VGAtuxiangxianshi
    用FPGA实现 VGA显示的图像显示控制器设计 用VHDL实现 硬件实现是屏幕上面出现彩色条纹(VGA display with FPGA image display controller design Using VHDL hardware implementation is colored stripes appear above the screen)
    2014-05-19 14:07:57下载
    积分:1
  • 05_fifo_test
    说明:  FIFO: First in, First out 代表先进的数据先出,后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO,根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)
    2021-04-08 22:19:20下载
    积分:1
  • I2C_CSDN
    verilog 编写的I2C程序,控制D/A的(I2C program written by Verilog to control D/A)
    2020-06-18 21:20:02下载
    积分:1
  • 测试74LS系列芯片功能是否正常
    可测试74LS00,74LS01,74LS02,74LS03等等芯片的功能是否正常。
    2022-07-16 01:45:40下载
    积分:1
  • SPI FLASH的控制器,FPGA实现,VHDL
    SPI FLASH的控制器,FPGA实现,VHDL 对于想使用FPGA实现spi flash控制的同学应该有用
    2022-03-23 23:56:51下载
    积分:1
  • 基于FPGA平台,实现了直接数字频率合成。
    基于FPGA平台,实现了直接数字频率合成。-FPGA-based platform, to achieve a direct digital frequency synthesis.
    2022-03-01 23:16:21下载
    积分:1
  • 24_Timer
    使用Verilog编写的24位定时器,具有apb 总线接口,可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
    2021-04-27 21:38:44下载
    积分:1
  • 利用vhdl编写的双端口Ram程序,不带数据纠错处理
    利用vhdl编写的双端口Ram程序,不带数据纠错处理-VHDL prepared to use dual-port Ram procedures, do not deal with data error correction
    2023-03-13 05:20:04下载
    积分:1
  • procedures major hardware description language (VHDL) to achieve : MCU and FPGA...
    程序主要用硬件描述语言(VHDL)实现: 单片机与FPGA接口通信的问题-procedures major hardware description language (VHDL) to achieve : MCU and FPGA interface communication problems
    2022-02-12 01:14:15下载
    积分:1
  • 696518资源总数
  • 106222会员总数
  • 14今日下载