登录
首页 » VHDL » vhdl code for alu and detemines the basic components of alu unit in cpu system

vhdl code for alu and detemines the basic components of alu unit in cpu system

于 2022-02-05 发布 文件大小:618.00 B
0 67
下载积分: 2 下载次数: 1

代码说明:

vhdl code for alu and detemines the basic components of alu unit in cpu system

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 基于sopc ep2c5开发板的时间标记服务例程
    基于sopc ep2c5开发板的时间标记服务例程-Sopc ep2c5 development board based on the time-stamping services routines
    2022-02-26 04:39:24下载
    积分:1
  • UART
    本代码用verilog语言配合sopc和nios实现了串口调试的目的。软件编程用C语言描述,只是比较简单的例子,适合初学者做了解用,本人亲自在EP2C8Q上实践。(The code to use verilog language sopc and nios achieved with serial debugging purposes. Software programming using C language description, but relatively simple example for beginners to do with understanding, I personally EP2C8Q on practice.)
    2013-09-11 10:48:17下载
    积分:1
  • cntl_ddr3(xilinx)
    xilinx ddr3最新VHDL代码,通过调试(xilinx ddr3 latest VHDL code through debugging)
    2007-12-05 23:03:10下载
    积分:1
  • uart(可综合)
    说明:  【实例简介】用Verilog实现uart串口协议,波特率可选9600、19200、38400、115200。8位数据为,1位校验位,1位停止位。 【实例截图】 【核心代码】核心代码包括TX,RX,Baud,FIFO([example introduction] UART serial port protocol is implemented with Verilog, and the baud rate can be 9600, 19200, 38400, 115200. 8-bit data, 1 bit check bit, 1 stop bit. [example screenshot] [core code] the core code includes TX, Rx, baud and FIFO)
    2020-12-08 16:00:16下载
    积分:1
  • pingpangqiu
    基于basys2的简单的乒乓球小游戏,通过ise13.4开发,使用语言VHDL,能够通过VGA在显示屏显示,能够实现双人对打,有计分功能。(Simple table tennis game, based on basys2 through ise13.4 development, using VHDL language, can through the VGA display shows, can achieve a double play, scoring function.)
    2014-07-04 01:42:00下载
    积分:1
  • ModelsimPDFWordPPT
    个人搜集的各类Modelsim教程全集视频PDFWordPPT等.rar(Personal collection of all kinds of Modelsim tutorial video PDFWordPPT Complete Works, etc.. Rar)
    2009-09-20 11:37:19下载
    积分:1
  • agc
    无线通信中接收侧自动增益控制模块的vhdl代码实现(Receive side of the AGC module vhdl code for wireless communications)
    2020-10-22 14:27:23下载
    积分:1
  • lesson38_lcd1602_clander
    基于Verilog语言编写的LCD1602显示的日历程序,类似时钟功能值得参考。(LCD1602 shows calendar program based on Verilog language, similar clock function is worth reference.)
    2019-05-26 09:29:18下载
    积分:1
  • Slave-FIFO
    详细讲解Slave FIFO模式下的初始化设置和相对应寄存器说明(Explain in detail the initial setup Slave FIFO mode and the corresponding register description)
    2014-03-18 17:33:23下载
    积分:1
  • 初学verilog HDL时 找的好资料 大家共享
    初学verilog HDL时 找的好资料 大家共享-Beginners should try to find a good share information
    2022-04-16 20:31:37下载
    积分:1
  • 696518资源总数
  • 104305会员总数
  • 11今日下载